588 lines
21 KiB
Scala
588 lines
21 KiB
Scala
// See LICENSE for license details.
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package uncore.agents
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import Chisel._
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.util._
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import cde.Parameters
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import scala.math.max
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class TrackerAllocation extends Bundle {
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val matches = Bool(OUTPUT)
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val can = Bool(OUTPUT)
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val should = Bool(INPUT)
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}
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trait HasTrackerAllocationIO extends Bundle {
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val alloc = new Bundle {
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val iacq = new TrackerAllocation
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val irel = new TrackerAllocation
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val oprb = new TrackerAllocation
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}
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}
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class ManagerXactTrackerIO(implicit p: Parameters) extends ManagerTLIO()(p)
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with HasTrackerAllocationIO
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class HierarchicalXactTrackerIO(implicit p: Parameters) extends HierarchicalTLIO()(p)
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with HasTrackerAllocationIO
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abstract class XactTracker(implicit p: Parameters) extends CoherenceAgentModule()(p)
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with HasXactTrackerStates
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with HasPendingBitHelpers {
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override val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_inner_probe :: s_outer_acquire :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 9)
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val state = Reg(init=s_idle)
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def quiesce(next: UInt = s_idle)(restore: => Unit) {
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all_pending_done := !scoreboard.foldLeft(Bool(false))(_||_)
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when(state === s_busy && all_pending_done) {
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state := next
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restore
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}
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}
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def pinAllReadyValidLow[T <: Data](b: Bundle) {
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b.elements.foreach {
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_._2 match {
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case d: DecoupledIO[_] =>
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if(d.ready.dir == OUTPUT) d.ready := Bool(false)
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else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
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case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case b: Bundle => pinAllReadyValidLow(b)
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case _ =>
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}
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}
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}
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}
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trait HasXactTrackerStates {
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def state: UInt
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def s_idle: UInt = UInt(0)
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def s_meta_read: UInt
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def s_meta_resp: UInt
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def s_wb_req: UInt
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def s_wb_resp: UInt
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def s_inner_probe: UInt
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def s_outer_acquire: UInt
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def s_busy: UInt
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def s_meta_write: UInt
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}
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trait HasPendingBitHelpers extends HasDataBeatCounters {
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val scoreboard = scala.collection.mutable.ListBuffer.empty[Bool]
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val all_pending_done = Wire(Bool())
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def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt =
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Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat)
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def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt =
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~Fill(in.tlDataBeats, dec) | ~UIntToOH(in.addr_beat)
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def addPendingBitWhenId[T <: HasClientId](inc: Bool, in: T): UInt =
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Fill(in.tlNCachingClients, inc) & UIntToOH(in.client_id)
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def dropPendingBitWhenId[T <: HasClientId](dec: Bool, in: T): UInt =
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~Fill(in.tlNCachingClients, dec) | ~UIntToOH(in.client_id)
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def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T], inc: Bool = Bool(true)): UInt =
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addPendingBitWhenBeat(in.fire() && in.bits.hasData() && inc, in.bits)
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def addPendingBitWhenBeatHasDataAndAllocs(
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in: DecoupledIO[AcquireFromSrc],
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alloc_override: Bool = Bool(false)): UInt =
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addPendingBitWhenBeatHasData(in, in.bits.allocate() || alloc_override)
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def addPendingBitWhenBeatNeedsRead(in: DecoupledIO[AcquireFromSrc], inc: Bool = Bool(true)): UInt = {
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val a = in.bits
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val needs_read = (a.isGet() || a.isAtomic() || a.hasPartialWritemask()) || inc
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addPendingBitWhenBeat(in.fire() && needs_read, a)
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}
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def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt =
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addPendingBitWhenBeat(in.fire() && in.bits.hasPartialWritemask(), in.bits)
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def addPendingBitsFromAcquire(a: SecondaryMissInfo): UInt =
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Mux(a.hasMultibeatData(), Fill(a.tlDataBeats, UInt(1, 1)), UIntToOH(a.addr_beat))
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def dropPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt =
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dropPendingBitWhenBeat(in.fire() && in.bits.hasData(), in.bits)
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def dropPendingBitAtDest[T <: HasId](in: DecoupledIO[T]): UInt =
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dropPendingBitWhenId(in.fire(), in.bits)
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def dropPendingBitAtDestWhenVoluntary[T <: HasId with MightBeVoluntary](in: DecoupledIO[T]): UInt =
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dropPendingBitWhenId(in.fire() && in.bits.isVoluntary(), in.bits)
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def addPendingBitAtSrc[T <: HasId](in: DecoupledIO[T]): UInt =
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addPendingBitWhenId(in.fire(), in.bits)
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def addPendingBitAtSrcWhenVoluntary[T <: HasId with MightBeVoluntary](in: DecoupledIO[T]): UInt =
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addPendingBitWhenId(in.fire() && in.bits.isVoluntary(), in.bits)
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def addOtherBits(en: Bool, nBits: Int): UInt =
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Mux(en, Cat(Fill(nBits - 1, UInt(1, 1)), UInt(0, 1)), UInt(0, nBits))
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def addPendingBitsOnFirstBeat(in: DecoupledIO[Acquire]): UInt =
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addOtherBits(in.fire() &&
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in.bits.hasMultibeatData() &&
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in.bits.addr_beat === UInt(0),
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in.bits.tlDataBeats)
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def dropPendingBitsOnFirstBeat(in: DecoupledIO[Acquire]): UInt =
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~addPendingBitsOnFirstBeat(in)
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}
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trait HasDataBuffer extends HasCoherenceAgentParameters {
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val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
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type TLDataBundle = TLBundle with HasTileLinkData with HasTileLinkBeatId
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def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) {
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when(in.fire() && in.bits.hasData() && alloc) {
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data_buffer(in.bits.addr_beat) := in.bits.data
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}
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}
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// TODO: provide func for accessing when innerDataBeats =/= outerDataBeats or internalDataBeats
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def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) {
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data_buffer(beat) := incoming
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}
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def mergeDataInner[T <: TLDataBundle](in: DecoupledIO[T]) {
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when(in.fire() && in.bits.hasData()) {
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mergeData(innerDataBits)(in.bits.addr_beat, in.bits.data)
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}
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}
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def mergeDataOuter[T <: TLDataBundle](in: DecoupledIO[T]) {
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when(in.fire() && in.bits.hasData()) {
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mergeData(outerDataBits)(in.bits.addr_beat, in.bits.data)
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}
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}
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}
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trait HasByteWriteMaskBuffer extends HasDataBuffer {
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val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerWriteMaskBits)))
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override def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) {
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when(in.fire() && in.bits.hasData() && alloc) {
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val beat = in.bits.addr_beat
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val full = FillInterleaved(8, in.bits.wmask())
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data_buffer(beat) := (~full & data_buffer(beat)) | (full & in.bits.data)
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wmask_buffer(beat) := in.bits.wmask() | wmask_buffer(beat) // assumes wmask_buffer is zeroed
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}
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}
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override def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) {
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val old_data = incoming // Refilled, written back, or de-cached data
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val new_data = data_buffer(beat) // Newly Put data is already in the buffer
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val wmask = FillInterleaved(8, wmask_buffer(beat))
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data_buffer(beat) := ~wmask & old_data | wmask & new_data
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}
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def clearWmaskBuffer() {
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wmask_buffer.foreach { w => w := UInt(0) }
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}
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}
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trait HasBlockAddressBuffer extends HasCoherenceAgentParameters {
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val xact_addr_block = Reg(init = UInt(0, width = blockAddrBits))
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}
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trait HasAcquireMetadataBuffer extends HasBlockAddressBuffer {
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val xact_allocate = Reg{ Bool() }
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val xact_amo_shift_bytes = Reg{ UInt() }
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val xact_op_code = Reg{ UInt() }
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val xact_addr_byte = Reg{ UInt() }
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val xact_op_size = Reg{ UInt() }
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val xact_addr_beat = Wire(UInt())
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val xact_iacq = Wire(new SecondaryMissInfo)
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}
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trait HasVoluntaryReleaseMetadataBuffer extends HasBlockAddressBuffer
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with HasPendingBitHelpers
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with HasXactTrackerStates {
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def io: HierarchicalXactTrackerIO
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val xact_vol_ir_r_type = Reg{ UInt() }
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val xact_vol_ir_src = Reg{ UInt() }
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val xact_vol_ir_client_xact_id = Reg{ UInt() }
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def xact_vol_irel = Release(
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src = xact_vol_ir_src,
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voluntary = Bool(true),
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r_type = xact_vol_ir_r_type,
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client_xact_id = xact_vol_ir_client_xact_id,
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addr_block = xact_addr_block)
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(p.alterPartial({ case TLId => p(InnerTLId) }))
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}
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trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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def inner_coh: ManagerMetadata
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val pending_irel_data = Reg(init=Bits(0, width = innerDataBeats))
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val vol_ignt_counter = Wire(new TwoWayBeatCounterStatus)
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def irel_can_merge: Bool
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def irel_same_xact: Bool
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def irel_is_allocating: Bool = state === s_idle && io.alloc.irel.should && io.inner.release.valid
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def irel_is_merging: Bool = (irel_can_merge || irel_same_xact) && io.inner.release.valid
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def innerRelease(block_vol_ignt: Bool = Bool(false), next: UInt = s_busy) {
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connectTwoWayBeatCounters(
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status = vol_ignt_counter,
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up = io.inner.release,
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down = io.inner.grant,
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trackUp = (r: Release) => {
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Mux(state === s_idle, io.alloc.irel.should, io.alloc.irel.matches) && r.isVoluntary() && r.requiresAck()
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},
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trackDown = (g: Grant) => (state =/= s_idle) && g.isVoluntary())
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when(irel_is_allocating) {
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xact_addr_block := io.irel().addr_block
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state := next
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}
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when(io.inner.release.fire()) {
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when(io.alloc.irel.should || (irel_can_merge && io.irel().first())) {
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xact_vol_ir_r_type := io.irel().r_type
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xact_vol_ir_src := io.irel().client_id
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xact_vol_ir_client_xact_id := io.irel().client_xact_id
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// If this release has data, set all the pending bits except the first.
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// Otherwise, clear all the pending bits
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pending_irel_data := Mux(io.irel().hasMultibeatData(),
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dropPendingBitWhenBeatHasData(io.inner.release),
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UInt(0))
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} .elsewhen (irel_same_xact) {
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pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release))
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}
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}
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io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) &&
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vol_ignt_counter.pending &&
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!(pending_irel_data.orR || block_vol_ignt)
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io.inner.grant.bits := inner_coh.makeGrant(xact_vol_irel)
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scoreboard += (pending_irel_data.orR, vol_ignt_counter.pending)
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}
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}
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trait EmitsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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val pending_orel_send = Reg(init=Bool(false))
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val pending_orel_data = Reg(init=Bits(0, width = innerDataBeats))
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val vol_ognt_counter = Wire(new TwoWayBeatCounterStatus)
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val pending_orel = pending_orel_send || pending_orel_data.orR || vol_ognt_counter.pending
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def outerRelease(
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coh: ClientMetadata,
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buffering: Bool = Bool(true),
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data: UInt = io.irel().data,
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add_pending_data_bits: UInt = UInt(0),
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add_pending_send_bit: Bool = Bool(false)) {
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when (state =/= s_idle || io.alloc.irel.should) {
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pending_orel_data := (pending_orel_data |
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addPendingBitWhenBeatHasData(io.inner.release) |
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add_pending_data_bits) &
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dropPendingBitWhenBeatHasData(io.outer.release)
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}
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when (add_pending_send_bit) { pending_orel_send := Bool(true) }
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when (io.outer.release.fire()) { pending_orel_send := Bool(false) }
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connectTwoWayBeatCounters(
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status = vol_ognt_counter,
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up = io.outer.release,
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down = io.outer.grant,
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trackUp = (r: Release) => r.isVoluntary() && r.requiresAck(),
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trackDown = (g: Grant) => g.isVoluntary())
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io.outer.release.valid := Mux(buffering,
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(state === s_busy) && Mux(io.orel().hasData(),
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pending_orel_data(vol_ognt_counter.up.idx),
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pending_orel_send),
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// only writebacks need to be forwarded to the outer interface
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(io.alloc.irel.should || io.alloc.irel.matches) &&
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io.irel().hasData() && io.inner.release.valid)
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io.outer.release.bits := coh.makeVoluntaryWriteback(
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client_xact_id = UInt(0), // TODO was tracker id, but not needed?
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addr_block = xact_addr_block,
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addr_beat = vol_ognt_counter.up.idx,
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data = data)
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when (vol_ognt_counter.pending) { io.outer.grant.ready := Bool(true) }
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scoreboard += (pending_orel, vol_ognt_counter.pending)
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}
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}
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trait EmitsInnerProbes extends HasBlockAddressBuffer
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with HasXactTrackerStates
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with HasPendingBitHelpers {
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def io: HierarchicalXactTrackerIO
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val needs_probes = (innerNCachingClients > 0)
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val pending_iprbs = Reg(UInt(width = max(innerNCachingClients, 1)))
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val curr_probe_dst = PriorityEncoder(pending_iprbs)
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def full_representation: UInt
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def initializeProbes() {
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if (needs_probes)
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pending_iprbs := full_representation & ~io.incoherent.toBits
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else
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pending_iprbs := UInt(0)
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}
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def irel_same_xact = io.irel().conflicts(xact_addr_block) &&
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!io.irel().isVoluntary() &&
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state === s_inner_probe
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def innerProbe(prb: Probe, next: UInt) {
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if (needs_probes) {
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val irel_counter = Wire(new TwoWayBeatCounterStatus)
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pending_iprbs := pending_iprbs & dropPendingBitAtDest(io.inner.probe)
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io.inner.probe.valid := state === s_inner_probe && pending_iprbs.orR
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io.inner.probe.bits := prb
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connectTwoWayBeatCounters(
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status = irel_counter,
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up = io.inner.probe,
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down = io.inner.release,
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max = innerNCachingClients,
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trackDown = (r: Release) => (state =/= s_idle) && !r.isVoluntary())
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when(state === s_inner_probe && !(pending_iprbs.orR || irel_counter.pending)) {
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state := next
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}
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} else {
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when (state === s_inner_probe) { state := next }
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}
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//N.B. no pending bits added to scoreboard because all handled in s_inner_probe
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}
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}
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trait RoutesInParent extends HasBlockAddressBuffer
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with HasXactTrackerStates {
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def io: HierarchicalXactTrackerIO
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type AddrComparison = HasCacheBlockAddress => Bool
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def exactAddrMatch(a: HasCacheBlockAddress): Bool = a.conflicts(xact_addr_block)
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def routeInParent(iacqMatches: AddrComparison = exactAddrMatch,
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irelMatches: AddrComparison = exactAddrMatch,
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oprbMatches: AddrComparison = exactAddrMatch) {
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io.alloc.iacq.matches := (state =/= s_idle) && iacqMatches(io.iacq())
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io.alloc.irel.matches := (state =/= s_idle) && irelMatches(io.irel())
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io.alloc.oprb.matches := (state =/= s_idle) && oprbMatches(io.oprb())
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io.alloc.iacq.can := state === s_idle
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io.alloc.irel.can := state === s_idle
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io.alloc.oprb.can := Bool(false)
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}
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}
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trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
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with AcceptsVoluntaryReleases
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with HasXactTrackerStates
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with HasPendingBitHelpers {
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def io: HierarchicalXactTrackerIO
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def nSecondaryMisses: Int
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def alwaysWriteFullBeat: Boolean
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def inner_coh: ManagerMetadata
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def trackerId: Int
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// Secondary miss queue holds transaction metadata used to make grants
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lazy val ignt_q = Module(new Queue(
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new SecondaryMissInfo()(p.alterPartial({ case TLId => p(InnerTLId) })),
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1 + nSecondaryMisses))
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val pending_ignt = Wire(Bool())
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val ignt_data_idx = Wire(UInt())
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val ignt_data_done = Wire(Bool())
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val ifin_counter = Wire(new TwoWayBeatCounterStatus)
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val pending_put_data = Reg(init=Bits(0, width = innerDataBeats))
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val pending_ignt_data = Reg(init=Bits(0, width = innerDataBeats))
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def iacq_same_xact: Bool = {
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(xact_iacq.client_xact_id === io.iacq().client_xact_id) &&
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xact_iacq.hasMultibeatData() &&
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pending_ignt &&
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pending_put_data(io.iacq().addr_beat)
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}
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def iacq_can_merge: Bool
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def iacq_is_allocating: Bool = state === s_idle && io.alloc.iacq.should && io.inner.acquire.valid
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def iacq_is_merging: Bool = (iacq_can_merge || iacq_same_xact) && io.inner.acquire.valid
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def innerAcquire(can_alloc: Bool, next: UInt) {
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// Enqueue some metadata information that we'll use to make coherence updates with later
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ignt_q.io.enq.valid := iacq_is_allocating || (iacq_is_merging && io.iacq().first())
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ignt_q.io.enq.bits := io.iacq()
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// Use the outputs of the queue to make further messages
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xact_iacq := Mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits)
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xact_addr_beat := xact_iacq.addr_beat
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pending_ignt := ignt_q.io.count > UInt(0)
|
|
|
|
// Track whether any beats are missing from a PutBlock
|
|
when (state =/= s_idle || io.alloc.iacq.should) {
|
|
pending_put_data := (pending_put_data &
|
|
dropPendingBitWhenBeatHasData(io.inner.acquire)) |
|
|
addPendingBitsOnFirstBeat(io.inner.acquire)
|
|
}
|
|
|
|
// Intialize transaction metadata for accepted Acquire
|
|
when(iacq_is_allocating) {
|
|
xact_addr_block := io.iacq().addr_block
|
|
xact_allocate := io.iacq().allocate() && can_alloc
|
|
xact_amo_shift_bytes := io.iacq().amo_shift_bytes()
|
|
xact_op_code := io.iacq().op_code()
|
|
xact_addr_byte := io.iacq().addr_byte()
|
|
xact_op_size := io.iacq().op_size()
|
|
// Make sure to collect all data from a PutBlock
|
|
pending_put_data := Mux(
|
|
io.iacq().isBuiltInType(Acquire.putBlockType),
|
|
dropPendingBitWhenBeatHasData(io.inner.acquire),
|
|
UInt(0))
|
|
pending_ignt_data := UInt(0)
|
|
state := next
|
|
}
|
|
|
|
scoreboard += (pending_put_data.orR)
|
|
}
|
|
|
|
def innerGrant(
|
|
data: UInt = io.ognt().data,
|
|
external_pending: Bool = Bool(false),
|
|
buffering: Bool = Bool(true),
|
|
add_pending_bits: UInt = UInt(0)) {
|
|
// Track the number of outstanding inner.finishes
|
|
connectTwoWayBeatCounters(
|
|
status = ifin_counter,
|
|
up = io.inner.grant,
|
|
down = io.inner.finish,
|
|
max = nSecondaryMisses,
|
|
trackUp = (g: Grant) => g.requiresAck())
|
|
|
|
// Track which beats are ready for response
|
|
when(!iacq_is_allocating) {
|
|
pending_ignt_data := (pending_ignt_data & dropPendingBitWhenBeatHasData(io.inner.grant)) |
|
|
addPendingBitWhenBeatHasData(io.inner.release) |
|
|
addPendingBitWhenBeatHasData(io.outer.grant) |
|
|
add_pending_bits
|
|
}
|
|
|
|
// Have we finished receiving the complete inner acquire transaction?
|
|
val iacq_finished = !(state === s_idle ||
|
|
state === s_meta_read ||
|
|
pending_put_data.orR)
|
|
|
|
val ignt_from_iacq = inner_coh.makeGrant(
|
|
sec = ignt_q.io.deq.bits,
|
|
manager_xact_id = UInt(trackerId),
|
|
data = data)
|
|
|
|
// Make the Grant message using the data stored in the secondary miss queue
|
|
val (cnt, done) = connectOutgoingDataBeatCounter(io.inner.grant, ignt_q.io.deq.bits.addr_beat)
|
|
ignt_data_idx := cnt
|
|
ignt_data_done := done
|
|
ignt_q.io.deq.ready := Bool(false)
|
|
when(!vol_ignt_counter.pending) {
|
|
ignt_q.io.deq.ready := ignt_data_done
|
|
io.inner.grant.bits := ignt_from_iacq
|
|
io.inner.grant.bits.addr_beat := ignt_data_idx // override based on outgoing counter
|
|
when (state === s_busy && pending_ignt) {
|
|
io.inner.grant.valid := !external_pending && Mux(buffering,
|
|
Mux(io.ignt().hasData(),
|
|
pending_ignt_data(ignt_data_idx), iacq_finished),
|
|
io.outer.grant.valid)
|
|
}
|
|
}
|
|
|
|
// We must wait for as many Finishes as we sent Grants
|
|
io.inner.finish.ready := state === s_busy
|
|
|
|
scoreboard += (pending_ignt, ifin_counter.pending)
|
|
}
|
|
|
|
}
|
|
|
|
trait EmitsOuterAcquires extends AcceptsInnerAcquires {
|
|
val ognt_counter = Wire(new TwoWayBeatCounterStatus)
|
|
|
|
// Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory:
|
|
//
|
|
// If we're allocating in this cache, we can use the current metadata
|
|
// to make an appropriate custom Acquire, otherwise we copy over the
|
|
// built-in Acquire from the inner TL to the outer TL
|
|
def outerAcquire(
|
|
caching: Bool,
|
|
coh: ClientMetadata,
|
|
block_outer_acquire: Bool = Bool(false),
|
|
buffering: Bool = Bool(true),
|
|
data: UInt = io.iacq().data,
|
|
wmask: UInt = io.iacq().wmask(),
|
|
next: UInt = s_busy) {
|
|
|
|
// Tracks outstanding Acquires, waiting for their matching Grant.
|
|
connectTwoWayBeatCounters(
|
|
status = ognt_counter,
|
|
up = io.outer.acquire,
|
|
down = io.outer.grant,
|
|
beat = xact_addr_beat,
|
|
trackDown = (g: Grant) => !g.isVoluntary())
|
|
|
|
io.outer.acquire.valid := state === s_outer_acquire &&
|
|
!block_outer_acquire &&
|
|
(xact_allocate ||
|
|
Mux(buffering,
|
|
!pending_put_data(ognt_counter.up.idx),
|
|
io.inner.acquire.valid))
|
|
|
|
io.outer.acquire.bits :=
|
|
Mux(caching,
|
|
coh.makeAcquire(
|
|
op_code = xact_op_code,
|
|
client_xact_id = UInt(0),
|
|
addr_block = xact_addr_block),
|
|
BuiltInAcquireBuilder(
|
|
a_type = xact_iacq.a_type,
|
|
client_xact_id = UInt(0),
|
|
addr_block = xact_addr_block,
|
|
addr_beat = ognt_counter.up.idx,
|
|
data = data,
|
|
addr_byte = xact_addr_byte,
|
|
operand_size = xact_op_size,
|
|
opcode = xact_op_code,
|
|
wmask = wmask,
|
|
alloc = Bool(false))
|
|
(p.alterPartial({ case TLId => p(OuterTLId)})))
|
|
|
|
when(state === s_outer_acquire && ognt_counter.up.done) { state := next }
|
|
|
|
when (ognt_counter.pending) { io.outer.grant.ready := Bool(true) }
|
|
|
|
scoreboard += ognt_counter.pending
|
|
}
|
|
}
|
|
|
|
abstract class VoluntaryReleaseTracker(val trackerId: Int)(implicit p: Parameters) extends XactTracker()(p)
|
|
with AcceptsVoluntaryReleases
|
|
with RoutesInParent {
|
|
def irel_can_merge = Bool(false)
|
|
def irel_same_xact = io.irel().conflicts(xact_addr_block) &&
|
|
io.irel().isVoluntary() &&
|
|
pending_irel_data.orR
|
|
}
|
|
|
|
abstract class AcquireTracker(val trackerId: Int)(implicit p: Parameters) extends XactTracker()(p)
|
|
with AcceptsInnerAcquires
|
|
with EmitsOuterAcquires
|
|
with EmitsInnerProbes
|
|
with RoutesInParent {
|
|
}
|