150 lines
5.2 KiB
Scala
150 lines
5.2 KiB
Scala
// See LICENSE for license details.
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package uncore.agents
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import Chisel._
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.constants._
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import cde.Parameters
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class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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// Create TSHRs for outstanding transactions
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val irelTrackerList =
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(0 until nReleaseTransactors).map(id =>
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Module(new BufferlessBroadcastVoluntaryReleaseTracker(id)))
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val iacqTrackerList =
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(nReleaseTransactors until nTransactors).map(id =>
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Module(new BufferlessBroadcastAcquireTracker(id)))
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val trackerList = irelTrackerList ++ iacqTrackerList
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// Propagate incoherence flags
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trackerList.map(_.io.incoherent) foreach { _ := io.incoherent }
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// Create an arbiter for the one memory port
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val outerList = trackerList.map(_.io.outer)
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val outer_arb = Module(new ClientTileLinkIOArbiter(outerList.size)
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(p.alterPartial({ case TLId => p(OuterTLId) })))
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outer_arb.io.in <> outerList
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io.outer <> outer_arb.io.out
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// Handle acquire transaction initiation
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val irel_vs_iacq_conflict =
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io.inner.acquire.valid &&
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io.inner.release.valid &&
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io.irel().conflicts(io.iacq())
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doInputRoutingWithAllocation(
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in = io.inner.acquire,
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outs = trackerList.map(_.io.inner.acquire),
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allocs = trackerList.map(_.io.alloc.iacq),
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allocOverride = Some(!irel_vs_iacq_conflict))
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io.outer.acquire.bits.data := io.inner.acquire.bits.data
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io.outer.acquire.bits.addr_beat := io.inner.acquire.bits.addr_beat
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// Handle releases, which might be voluntary and might have data
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doInputRoutingWithAllocation(
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in = io.inner.release,
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outs = trackerList.map(_.io.inner.release),
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allocs = trackerList.map(_.io.alloc.irel))
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io.outer.release.bits.data := io.inner.release.bits.data
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io.outer.release.bits.addr_beat := io.inner.release.bits.addr_beat
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// Wire probe requests and grant reply to clients, finish acks from clients
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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io.inner.grant.bits.data := io.outer.grant.bits.data
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io.inner.grant.bits.addr_beat := io.outer.grant.bits.addr_beat
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doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
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}
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class BufferlessBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
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extends BroadcastVoluntaryReleaseTracker(trackerId)(p) {
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// Tell the parent if any incoming messages conflict with the ongoing transaction
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routeInParent()
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io.alloc.iacq.can := Bool(false)
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// Start transaction by accepting inner release
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innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending)
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// A release beat can be accepted if we are idle, if its a mergeable transaction, or if its a tail beat
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// and if the outer relase path is clear
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val irel_could_accept = state === s_idle || irel_can_merge || irel_same_xact
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io.inner.release.ready := irel_could_accept &&
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(!io.irel().hasData() || io.outer.release.ready)
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// Dispatch outer release
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outerRelease(coh = outer_coh.onHit(M_XWR), buffering = Bool(false))
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quiesce() {}
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}
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class BufferlessBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
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extends BroadcastAcquireTracker(trackerId)(p) {
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// Setup IOs used for routing in the parent
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routeInParent()
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io.alloc.irel.can := Bool(false)
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// First, take care of accpeting new acquires or secondary misses
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// Handling of primary and secondary misses' data and write mask merging
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innerAcquire(
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can_alloc = Bool(false),
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next = s_inner_probe)
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val iacq_could_accept = state === s_outer_acquire || iacq_can_merge || iacq_same_xact
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io.inner.acquire.ready := iacq_could_accept &&
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(!io.iacq().hasData() || io.outer.acquire.fire())
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// Track which clients yet need to be probed and make Probe message
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innerProbe(
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inner_coh.makeProbe(curr_probe_dst, xact_iacq, xact_addr_block),
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s_outer_acquire)
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// Handle incoming releases from clients, which may reduce sharer counts
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// and/or write back dirty data, and may be unexpected voluntary releases
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def irel_can_merge = io.irel().conflicts(xact_addr_block) &&
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io.irel().isVoluntary() &&
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!vol_ignt_counter.pending &&
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(state =/= s_idle)
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innerRelease(block_vol_ignt = vol_ognt_counter.pending)
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val irel_could_accept = irel_can_merge || irel_same_xact
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io.inner.release.ready := irel_could_accept &&
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(!io.irel().hasData() || io.outer.release.ready)
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// If there was a writeback, forward it outwards
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outerRelease(
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coh = outer_coh.onHit(M_XWR),
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buffering = Bool(false))
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// Send outer request for miss
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outerAcquire(
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caching = !xact_iacq.isBuiltInType(),
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block_outer_acquire = vol_ognt_counter.pending,
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buffering = Bool(false),
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coh = outer_coh,
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next = s_busy)
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// Handle the response from outer memory
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when (ognt_counter.pending && io.ognt().hasData()) {
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io.outer.grant.ready := io.inner.grant.ready // bypass data
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}
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// Acknowledge or respond with data
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innerGrant(
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external_pending = pending_orel || vol_ognt_counter.pending,
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buffering = Bool(false))
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when(iacq_is_allocating) { initializeProbes() }
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// Wait for everything to quiesce
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quiesce() {}
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}
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