ed827678ac
This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
81 lines
2.0 KiB
Verilog
81 lines
2.0 KiB
Verilog
// See LICENSE for license details.
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import "DPI-C" function int debug_tick
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(
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output bit debug_req_valid,
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input bit debug_req_ready,
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output int debug_req_bits_addr,
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output int debug_req_bits_op,
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output longint debug_req_bits_data,
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input bit debug_resp_valid,
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output bit debug_resp_ready,
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input int debug_resp_bits_resp,
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input longint debug_resp_bits_data
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);
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module SimDTM(
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input clk,
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input reset,
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output debug_req_valid,
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input debug_req_ready,
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output [ 4:0] debug_req_bits_addr,
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output [ 1:0] debug_req_bits_op,
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output [33:0] debug_req_bits_data,
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input debug_resp_valid,
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output debug_resp_ready,
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input [ 1:0] debug_resp_bits_resp,
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input [33:0] debug_resp_bits_data,
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output [31:0] exit
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);
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bit r_reset;
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wire #0.1 __debug_req_ready = debug_req_ready;
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wire #0.1 __debug_resp_valid = debug_resp_valid;
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wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
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wire [63:0] #0.1 __debug_resp_bits_data = {30'b0, debug_resp_bits_data};
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bit __debug_req_valid;
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int __debug_req_bits_addr;
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int __debug_req_bits_op;
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longint __debug_req_bits_data;
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bit __debug_resp_ready;
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int __exit;
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assign #0.1 debug_req_valid = __debug_req_valid;
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assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[4:0];
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assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
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assign #0.1 debug_req_bits_data = __debug_req_bits_data[33:0];
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assign #0.1 debug_resp_ready = __debug_resp_ready;
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assign #0.1 exit = __exit;
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always @(posedge clk)
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begin
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r_reset <= reset;
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if (reset || r_reset)
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begin
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__debug_req_valid = 0;
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__debug_resp_ready = 0;
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__exit = 0;
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end
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else
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begin
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__exit = debug_tick(
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__debug_req_valid,
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__debug_req_ready,
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__debug_req_bits_addr,
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__debug_req_bits_op,
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__debug_req_bits_data,
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__debug_resp_valid,
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__debug_resp_ready,
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__debug_resp_bits_resp,
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__debug_resp_bits_data
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);
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end
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end
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endmodule
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