146 lines
4.4 KiB
Scala
146 lines
4.4 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.util.LFSR16
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import junctions.unittests._
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object LFSR64
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{
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private var counter = 0
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private def next: Int = {
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counter += 1
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counter
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}
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def apply(increment: Bool = Bool(true), seed: Int = next): UInt =
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{
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val wide = 64
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val lfsr = RegInit(UInt((seed * 0xDEADBEEFCAFEBAB1L) >>> 1, width = wide))
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val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4)
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when (increment) { lfsr := Cat(xor, lfsr(wide-1,1)) }
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lfsr
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}
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}
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object NoiseMaker
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{
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def apply(wide: Int, increment: Bool = Bool(true)): UInt = {
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val lfsrs = Seq.fill((wide+63)/64) { LFSR64(increment) }
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Cat(lfsrs)(wide-1,0)
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}
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}
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object MaskMaker
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{
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def apply(wide: Int, bits: UInt): UInt =
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Vec.tabulate(wide) {UInt(_) < bits} .asUInt
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}
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class TLFuzzer(nOperations: Int) extends LazyModule
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{
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val node = TLClientNode(TLClientParameters())
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val finished = Bool()
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}
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val out = io.out(0)
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val edge = node.edgesOut(0)
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val idx = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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val finished = RegInit(Bool(false))
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val valid = RegInit(Bool(false))
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valid := Bool(true)
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io.finished := finished
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val counter = RegInit(UInt(0, width = log2Up(edge.maxTransfer)))
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val inc = Wire(Bool())
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val addrBits = log2Up(edge.manager.maxAddress + 1)
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val amo_size = UInt(2) + NoiseMaker(1, inc) // word or dword
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val size = NoiseMaker(edge.bundle.sizeBits, inc)
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val addr_mask = MaskMaker(addrBits, size)
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val addr = NoiseMaker(addrBits, inc) & ~addr_mask
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val wmask = NoiseMaker(edge.manager.beatBytes, inc)
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val data = NoiseMaker(edge.bundle.dataBits, inc)
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val arth_op = NoiseMaker(3, inc)
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val log_op = NoiseMaker(2, inc)
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val src = UInt(0)
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val (glegal, gbits) = edge.Get(src, addr, size)
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val (pflegal, pfbits) = if(edge.manager.anySupportPutFull) {
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edge.Put(src, addr, size, data)
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} else { (glegal, gbits) }
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val (pplegal, ppbits) = if(edge.manager.anySupportPutPartial) {
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edge.Put(src, addr, size, data, wmask)
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} else { (glegal, gbits) }
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val (alegal, abits) = if(edge.manager.anySupportArithmetic) {
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edge.Arithmetic(src, addr, size, data, arth_op)
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} else { (glegal, gbits) }
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val (llegal, lbits) = if(edge.manager.anySupportLogical) {
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edge.Logical(src, addr, size, data, log_op)
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} else { (glegal, gbits) }
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val (hlegal, hbits) = if(edge.manager.anySupportHint) {
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edge.Hint(src, addr, size, UInt(0))
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} else { (glegal, gbits) }
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val a_type_sel = NoiseMaker(3, inc)
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val legal = MuxLookup(a_type_sel, glegal, Seq(
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UInt("b000") -> glegal,
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UInt("b001") -> pflegal,
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UInt("b010") -> pplegal,
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UInt("b011") -> alegal,
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UInt("b100") -> llegal,
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UInt("b101") -> hlegal))
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val bits = MuxLookup(a_type_sel, gbits, Seq(
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UInt("b000") -> gbits,
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UInt("b001") -> pfbits,
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UInt("b010") -> ppbits,
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UInt("b011") -> abits,
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UInt("b100") -> lbits,
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UInt("b101") -> hbits))
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out.a.valid := legal
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out.a.bits := bits
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.d.ready := Bool(true)
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out.e.valid := Bool(false)
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inc := !legal || (out.a.fire() && counter === UInt(0))
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when (out.a.fire()) {
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counter := counter - UInt(1)
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when (counter === UInt(0)) {
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counter := edge.numBeats(out.a.bits) - UInt(1)
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idx := idx - UInt(1)
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}
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when (idx === UInt(0)) { finished := Bool(true) }
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}
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}
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}
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class TLFuzzRAM extends LazyModule
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{
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val ram = LazyModule(new TLRAM(AddressSet(0, 0xfff)))
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val xbar = LazyModule(new TLXbar)
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val fuzz = LazyModule(new TLFuzzer(1000))
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connect(TLWidthWidget(TLHintHandler(fuzz.node), 16) -> xbar.node)
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connect(TLFragmenter(TLBuffer(xbar.node), 4, 256) -> ram.node)
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLFuzzRAMTest extends UnitTest {
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val dut = LazyModule(new TLFuzzRAM).module
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io.finished := dut.io.finished
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}
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