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riscv/rocket-chip
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063ca0ed4aeae602d4089f358ced1584bbb527c9
rocket-chip/scripts
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Andrew Waterman 31b75987ca Avoid width warning
2017-08-08 20:57:31 -07:00
..
debug_rom
debug: Use flags for resume instead of program buffer. Untested.
2017-04-07 16:47:16 -07:00
.gitignore
add makefile for float_fix and comlog tools
2016-02-29 11:24:53 -08:00
authors
scripts/authors: Matthew Naylor's submissions were under Berkeley terms
2016-11-27 22:15:43 -08:00
check_cache_trace.py
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
check_comparator_trace.py
add a script for checking comparator trace
2016-07-12 14:42:04 -07:00
copyright-file
scripts: two scripts to determine copyright holder of files
2016-11-27 22:15:38 -08:00
Makefile
add makefile for float_fix and comlog tools
2016-02-29 11:24:53 -08:00
modify-copyright
scripts: two scripts to determine copyright holder of files
2016-11-27 22:15:38 -08:00
toaxe.py
move groundtest/scripts to top-level scripts/
2016-07-28 11:36:55 -07:00
tracegen.py
[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)
2017-01-25 12:10:49 -08:00
tracegen+check.sh
get TraceGen working again
2016-09-26 17:28:21 -07:00
tracestats.py
move groundtest/scripts to top-level scripts/
2016-07-28 11:36:55 -07:00
vlsi_mem_gen
Avoid width warning
2017-08-08 20:57:31 -07:00
vlsi_rom_gen
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
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