400 lines
16 KiB
Scala
400 lines
16 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
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{
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val io = new Bundle {
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val addr = UFix(INPUT, log2Up(n))
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val en = Bool(INPUT)
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val rw = Bool(INPUT)
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val wdata = gen.asInput
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val wmask = gen.asInput
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val rdata = gen.asOutput
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}
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require(readLatency >= 0 && readLatency <= 2)
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val data = gen
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val colMux = if (2*data.width <= leaf.data.width && n > leaf.n) 1 << math.floor(math.log(leaf.data.width/data.width)/math.log(2)).toInt else 1
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val nWide = if (data.width > leaf.data.width) 1+(data.width-1)/leaf.data.width else 1
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val nDeep = if (n > colMux*leaf.n) 1+(n-1)/(colMux*leaf.n) else 1
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if (nDeep > 1 || colMux > 1)
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require(isPow2(n) && isPow2(leaf.n))
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val idx = io.addr(log2Up(n/nDeep/colMux)-1, 0)
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val rdataDeep = Vec(nDeep) { Bits() }
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val rdataSel = Vec(nDeep) { Bool() }
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val cond = Vec(nDeep) { Bool() }
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val ren = Vec(nDeep) { Bool() }
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val reg_ren = Vec(nDeep) { Reg() { Bool() } }
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val reg2_ren = Vec(nDeep) { Reg() { Bool() } }
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val reg_raddr = Vec(nDeep) { Reg() { UFix() } }
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val reg2_raddr = Vec(nDeep) { Reg() { UFix() } }
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val renOut = Vec(nDeep) { Bool() }
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val raddrOut = Vec(nDeep) { UFix() }
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val rdata = Vec(nDeep) { Vec(nWide) { Bits() } }
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val wdata = io.wdata.toBits
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val wmask = io.wmask.toBits
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for (i <- 0 until nDeep) {
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cond(i) := (if (nDeep == 1) io.en else io.en && UFix(i) === io.addr(log2Up(n)-1, log2Up(n/nDeep)))
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ren(i) := cond(i) && !io.rw
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reg_ren(i) := ren(i)
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reg2_ren(i) := reg_ren(i)
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when (ren(i)) { reg_raddr(i) := io.addr }
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when (reg_ren(i)) { reg2_raddr(i) := reg_raddr(i) }
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renOut(i) := (if (readLatency > 1) reg2_ren(i) else if (readLatency > 0) reg_ren(i) else ren(i))
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raddrOut(i) := (if (readLatency > 1) reg2_raddr(i) else if (readLatency > 0) reg_raddr(i) else io.addr)
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for (j <- 0 until nWide) {
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val mem = leaf.clone
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var dout: Bits = null
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val dout1 = if (readLatency > 0) Reg() { Bits() } else null
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var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.width*(j+1))-1, leaf.data.width*j))
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if (colMux > 1)
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wmask0 = wmask0 & FillInterleaved(gen.width, UFixToOH(io.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
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val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.width*(j+1))-1, leaf.data.width*j))
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when (cond(i)) {
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when (io.rw) { mem.write(idx, wdata0, wmask0) }
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.otherwise { if (readLatency > 0) dout1 := mem(idx) }
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}
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if (readLatency == 0) {
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dout = mem(idx)
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} else if (readLatency == 1) {
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dout = dout1
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} else {
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val dout2 = Reg() { Bits() }
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when (reg_ren(i)) { dout2 := dout1 }
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dout = dout2
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}
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rdata(i)(j) := dout
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}
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val rdataWide = rdata(i).reduceLeft((x, y) => Cat(y, x))
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var colMuxOut = rdataWide
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if (colMux > 1) {
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val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.width*(k+1)-1, gen.width*k))) { Bits() }
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colMuxOut = colMuxIn(raddrOut(i)(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
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}
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rdataDeep(i) := colMuxOut
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rdataSel(i) := renOut(i)
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}
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io.rdata := Mux1H(rdataSel, rdataDeep)
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}
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class LLCDataReq(ways: Int) extends MemReqCmd
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{
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val way = UFix(width = log2Up(ways))
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val isWriteback = Bool()
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override def clone = new LLCDataReq(ways).asInstanceOf[this.type]
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}
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class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
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{
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val io = new Bundle {
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val cpu = (new FIFOIO) { new MemReqCmd }.flip
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val repl_way = UFix(INPUT, log2Up(ways))
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val repl_dirty = Bool(INPUT)
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val repl_tag = UFix(INPUT, PADDR_BITS - OFFSET_BITS - log2Up(sets))
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val data = (new FIFOIO) { new LLCDataReq(ways) }
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val tag = (new FIFOIO) { new Bundle {
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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val way = UFix(width = log2Up(ways))
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} }
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val mem = new ioMemPipe
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val mem_resp_set = UFix(OUTPUT, log2Up(sets))
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val mem_resp_way = UFix(OUTPUT, log2Up(ways))
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}
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class MSHR extends Bundle {
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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val way = UFix(width = log2Up(ways))
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val tag = io.cpu.bits.tag.clone
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val refilled = Bool()
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val refillCount = UFix(width = log2Up(REFILL_CYCLES))
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val requested = Bool()
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val old_dirty = Bool()
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val old_tag = UFix(width = PADDR_BITS - OFFSET_BITS - log2Up(sets))
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override def clone = new MSHR().asInstanceOf[this.type]
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}
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val valid = Vec(outstanding) { Reg(resetVal = Bool(false)) }
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val validBits = valid.toBits
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val freeId = PriorityEncoder(~validBits)
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val mshr = Vec(outstanding) { Reg() { new MSHR } }
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when (io.cpu.valid && io.cpu.ready) {
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valid(freeId) := Bool(true)
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mshr(freeId).addr := io.cpu.bits.addr
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mshr(freeId).tag := io.cpu.bits.tag
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mshr(freeId).way := io.repl_way
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mshr(freeId).old_dirty := io.repl_dirty
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mshr(freeId).old_tag := io.repl_tag
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mshr(freeId).requested := Bool(false)
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mshr(freeId).refillCount := UFix(0)
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mshr(freeId).refilled := Bool(false)
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}
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val requests = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && !mshr(i).old_dirty && !mshr(i).requested):_*)
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val request = requests.orR
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val requestId = PriorityEncoder(requests)
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when (io.mem.req_cmd.valid && io.mem.req_cmd.ready) { mshr(requestId).requested := Bool(true) }
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val refillId = io.mem.resp.bits.tag(log2Up(outstanding)-1, 0)
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val refillCount = mshr(refillId).refillCount
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when (io.mem.resp.valid) {
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mshr(refillId).refillCount := refillCount + UFix(1)
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when (refillCount === UFix(REFILL_CYCLES-1)) { mshr(refillId).refilled := Bool(true) }
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}
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val replays = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && mshr(i).refilled):_*)
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val replay = replays.orR
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val replayId = PriorityEncoder(replays)
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when (replay && io.data.ready && io.tag.ready) { valid(replayId) := Bool(false) }
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val writebacks = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && mshr(i).old_dirty):_*)
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val writeback = writebacks.orR
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val writebackId = PriorityEncoder(writebacks)
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when (writeback && io.data.ready && !replay) { mshr(writebackId).old_dirty := Bool(false) }
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val conflicts = Cat(Bits(0), (0 until outstanding).map(i => valid(i) && io.cpu.bits.addr(log2Up(sets)-1, 0) === mshr(i).addr(log2Up(sets)-1, 0)):_*)
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io.cpu.ready := !conflicts.orR && !validBits.andR
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io.data.valid := replay && io.tag.ready || writeback
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io.data.bits.rw := Bool(false)
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io.data.bits.tag := mshr(replayId).tag
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io.data.bits.isWriteback := Bool(true)
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io.data.bits.addr := Cat(mshr(writebackId).old_tag, mshr(writebackId).addr(log2Up(sets)-1, 0)).toUFix
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io.data.bits.way := mshr(writebackId).way
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when (replay) {
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io.data.bits.isWriteback := Bool(false)
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io.data.bits.addr := mshr(replayId).addr
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io.data.bits.way := mshr(replayId).way
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}
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io.tag.valid := replay && io.data.ready
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io.tag.bits.addr := io.data.bits.addr
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io.tag.bits.way := io.data.bits.way
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io.mem.req_cmd.valid := request
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io.mem.req_cmd.bits.rw := Bool(false)
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io.mem.req_cmd.bits.addr := mshr(requestId).addr
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io.mem.req_cmd.bits.tag := requestId
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io.mem_resp_set := mshr(refillId).addr
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io.mem_resp_way := mshr(refillId).way
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}
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class LLCWriteback(requestors: Int) extends Component
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{
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val io = new Bundle {
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val req = Vec(requestors) { (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }.flip }
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val data = Vec(requestors) { (new FIFOIO) { new MemData }.flip }
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val mem = new ioMemPipe
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}
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val valid = Reg(resetVal = Bool(false))
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val who = Reg() { UFix() }
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val addr = Reg() { UFix() }
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val cmd_sent = Reg() { Bool() }
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val data_sent = Reg() { Bool() }
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val count = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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var anyReq = Bool(false)
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for (i <- 0 until requestors) {
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io.req(i).ready := !valid && !anyReq
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io.data(i).ready := valid && who === UFix(i) && io.mem.req_data.ready
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anyReq = anyReq || io.req(i).valid
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}
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val nextWho = PriorityEncoder(io.req.map(_.valid))
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when (!valid && io.req.map(_.valid).reduceLeft(_||_)) {
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valid := Bool(true)
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cmd_sent := Bool(false)
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data_sent := Bool(false)
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who := nextWho
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addr := io.req(nextWho).bits
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}
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when (io.mem.req_data.valid && io.mem.req_data.ready) {
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count := count + UFix(1)
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when (count === UFix(REFILL_CYCLES-1)) {
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data_sent := Bool(true)
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when (cmd_sent) { valid := Bool(false) }
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}
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}
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when (io.mem.req_cmd.valid && io.mem.req_cmd.ready) { cmd_sent := Bool(true) }
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when (valid && cmd_sent && data_sent) { valid := Bool(false) }
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io.mem.req_cmd.valid := valid && !cmd_sent
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io.mem.req_cmd.bits.addr := addr
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io.mem.req_cmd.bits.rw := Bool(true)
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io.mem.req_data.valid := valid && !data_sent && io.data(who).valid
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io.mem.req_data.bits := io.data(who).bits
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}
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class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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{
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val io = new Bundle {
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val req = (new FIFOIO) { new LLCDataReq(ways) }.flip
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val req_data = (new FIFOIO) { new MemData }.flip
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val writeback = (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }
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val writeback_data = (new FIFOIO) { new MemData }
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val resp = (new FIFOIO) { new MemResp }
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val mem_resp = (new PipeIO) { new MemResp }.flip
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val mem_resp_set = UFix(INPUT, log2Up(sets))
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val mem_resp_way = UFix(INPUT, log2Up(ways))
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}
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val data = new BigMem(sets*ways*REFILL_CYCLES, 2, leaf)(Bits(width = MEM_DATA_BITS))
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class QEntry extends MemResp {
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val isWriteback = Bool()
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override def clone = new QEntry().asInstanceOf[this.type]
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}
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val q = (new queue(4)) { new QEntry }
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val qReady = q.io.count <= UFix(q.entries - 3)
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val valid = Reg(resetVal = Bool(false))
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val req = Reg() { io.req.bits.clone }
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val count = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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val refillCount = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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when (data.io.en && !io.mem_resp.valid) {
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count := count + UFix(1)
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when (valid && count === UFix(REFILL_CYCLES-1)) { valid := Bool(false) }
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}
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when (io.req.valid && io.req.ready) { valid := Bool(true); req := io.req.bits }
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when (io.mem_resp.valid) { refillCount := refillCount + UFix(1) }
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data.io.en := io.req.valid && io.req.ready && Mux(io.req.bits.rw, io.req_data.valid, qReady)
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data.io.addr := Cat(io.req.bits.way, io.req.bits.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.rw := io.req.bits.rw
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data.io.wdata := io.req_data.bits.data
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data.io.wmask := Fix(-1, io.req_data.bits.data.width)
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when (valid) {
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data.io.en := Mux(req.rw, io.req_data.valid, qReady)
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data.io.addr := Cat(req.way, req.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.rw := req.rw
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}
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when (io.mem_resp.valid) {
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data.io.en := Bool(true)
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data.io.addr := Cat(io.mem_resp_way, io.mem_resp_set, refillCount).toUFix
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data.io.rw := Bool(true)
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data.io.wdata := io.mem_resp.bits.data
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}
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q.io.enq.valid := Reg(Reg(data.io.en && !data.io.rw, resetVal = Bool(false)), resetVal = Bool(false))
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q.io.enq.bits.tag := Reg(Reg(Mux(valid, req.tag, io.req.bits.tag)))
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q.io.enq.bits.data := data.io.rdata
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q.io.enq.bits.isWriteback := Reg(Reg(Mux(valid, req.isWriteback, io.req.bits.isWriteback)))
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io.req.ready := !valid && Mux(io.req.bits.isWriteback, io.writeback.ready, Bool(true))
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io.req_data.ready := !io.mem_resp.valid && Mux(valid, req.rw, io.req.valid && io.req.bits.rw)
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io.writeback.valid := io.req.valid && io.req.ready && io.req.bits.isWriteback
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io.writeback.bits := io.req.bits.addr
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q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, io.resp.ready)
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io.resp.valid := q.io.deq.valid && !q.io.deq.bits.isWriteback
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io.resp.bits := q.io.deq.bits
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io.writeback_data.valid := q.io.deq.valid && q.io.deq.bits.isWriteback
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io.writeback_data.bits := q.io.deq.bits
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}
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class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], dataLeaf: Mem[Bits]) extends Component
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{
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val io = new Bundle {
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val cpu = new ioMem().flip
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val mem = new ioMemPipe
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}
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val tagWidth = PADDR_BITS - OFFSET_BITS - log2Up(sets)
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val metaWidth = tagWidth + 2 // valid + dirty
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val memCmdArb = (new Arbiter(2)) { new MemReqCmd }
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val dataArb = (new Arbiter(2)) { new LLCDataReq(ways) }
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val mshr = new LLCMSHRFile(sets, ways, outstanding)
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val tags = new BigMem(sets, 1, tagLeaf)(Bits(width = metaWidth*ways))
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val data = new LLCData(sets, ways, dataLeaf)
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val writeback = new LLCWriteback(2)
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val initCount = Reg(resetVal = UFix(0, log2Up(sets+1)))
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val initialize = !initCount(log2Up(sets))
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when (initialize) { initCount := initCount + UFix(1) }
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val stall_s1 = Bool()
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val replay_s1 = Reg(resetVal = Bool(false))
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val s1_valid = Reg(io.cpu.req_cmd.valid && !stall_s1 || replay_s1, resetVal = Bool(false))
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replay_s1 := s1_valid && stall_s1
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val s1 = Reg() { new MemReqCmd }
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when (io.cpu.req_cmd.valid && io.cpu.req_cmd.ready) { s1 := io.cpu.req_cmd.bits }
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val stall_s2 = Bool()
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val s2_valid = Reg(resetVal = Bool(false))
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s2_valid := s1_valid && !replay_s1 && !stall_s1 || stall_s2
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val s2 = Reg() { new MemReqCmd }
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val s2_tags = Vec(ways) { Reg() { Bits(width = metaWidth) } }
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when (s1_valid && !stall_s1 && !replay_s1) {
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s2 := s1
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for (i <- 0 until ways)
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s2_tags(i) := tags.io.rdata(metaWidth*(i+1)-1, metaWidth*i)
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}
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val s2_hits = s2_tags.map(t => t(tagWidth) && s2.addr(s2.addr.width-1, s2.addr.width-tagWidth) === t(tagWidth-1, 0))
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val s2_hit_way = OHToUFix(s2_hits)
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val s2_hit = s2_hits.reduceLeft(_||_)
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val s2_hit_dirty = s2_tags(s2_hit_way)(tagWidth+1)
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val repl_way = LFSR16(s2_valid)(log2Up(ways)-1, 0)
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val repl_tag = s2_tags(repl_way).toUFix
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val setDirty = s2_valid && s2.rw && s2_hit && !s2_hit_dirty
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stall_s1 := initialize || mshr.io.tag.valid || setDirty || s2_valid && !s2_hit || stall_s2
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tags.io.en := (io.cpu.req_cmd.valid || replay_s1) && !stall_s1 || initialize || setDirty || mshr.io.tag.valid
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tags.io.addr := Mux(initialize, initCount, Mux(setDirty, s2.addr, Mux(mshr.io.tag.valid, mshr.io.tag.bits.addr, Mux(replay_s1, s1.addr, io.cpu.req_cmd.bits.addr)))(log2Up(sets)-1,0))
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tags.io.rw := initialize || setDirty || mshr.io.tag.valid
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tags.io.wdata := Mux(initialize, UFix(0), Fill(ways, Cat(setDirty, Bool(true), Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.width-1, mshr.io.tag.bits.addr.width-tagWidth))))
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tags.io.wmask := FillInterleaved(metaWidth, Mux(initialize, Fix(-1, ways), UFixToOH(Mux(setDirty, s2_hit_way, mshr.io.tag.bits.way))))
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mshr.io.cpu.valid := s2_valid && !s2_hit && !s2.rw
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mshr.io.cpu.bits := s2
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mshr.io.repl_way := repl_way
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mshr.io.repl_dirty := repl_tag(tagWidth+1, tagWidth).andR
|
|
mshr.io.repl_tag := repl_tag
|
|
mshr.io.mem.resp := io.mem.resp
|
|
mshr.io.tag.ready := !setDirty
|
|
|
|
data.io.req <> dataArb.io.out
|
|
data.io.mem_resp := io.mem.resp
|
|
data.io.mem_resp_set := mshr.io.mem_resp_set
|
|
data.io.mem_resp_way := mshr.io.mem_resp_way
|
|
data.io.req_data.bits := io.cpu.req_data.bits
|
|
|
|
writeback.io.req(0) <> data.io.writeback
|
|
writeback.io.data(0) <> data.io.writeback_data
|
|
writeback.io.req(1).valid := s2_valid && !s2_hit && s2.rw
|
|
writeback.io.req(1).bits := s2.addr
|
|
writeback.io.data(1).valid := io.cpu.req_data.valid
|
|
writeback.io.data(1).bits := io.cpu.req_data.bits
|
|
data.io.req_data.valid := io.cpu.req_data.valid && !writeback.io.data(1).ready
|
|
|
|
memCmdArb.io.in(0) <> mshr.io.mem.req_cmd
|
|
memCmdArb.io.in(1) <> writeback.io.mem.req_cmd
|
|
|
|
dataArb.io.in(0) <> mshr.io.data
|
|
dataArb.io.in(1).valid := s2_valid && s2_hit
|
|
dataArb.io.in(1).bits := s2
|
|
dataArb.io.in(1).bits.way := s2_hit_way
|
|
dataArb.io.in(1).bits.isWriteback := Bool(false)
|
|
|
|
stall_s2 := s2_valid && !Mux(s2_hit, dataArb.io.in(1).ready, Mux(s2.rw, writeback.io.req(1).ready, mshr.io.cpu.ready))
|
|
|
|
io.cpu.resp <> data.io.resp
|
|
io.cpu.req_cmd.ready := !stall_s1 && !replay_s1
|
|
io.cpu.req_data.ready := writeback.io.data(1).ready || data.io.req_data.ready
|
|
io.mem.req_cmd <> memCmdArb.io.out
|
|
io.mem.req_data <> writeback.io.mem.req_data
|
|
}
|