01ca3efc2b
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
85 lines
3.3 KiB
Scala
85 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.system
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import Chisel._
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import freechips.rocketchip.config.Config
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => {
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// DTS descriptive parameters
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case DTSModel => "freechips,rocketchip-unknown"
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case DTSCompat => Nil
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case DTSTimebase => BigInt(1000000) // 1 MHz
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case RTCPeriod => Some(1000) // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
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// External port parameters
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case IncludeJtagDTM => false
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case JtagDTMKey => new JtagDTMKeyDefault()
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case NExtTopInterrupts => 2
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case ExtMem => MasterPortParams(
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base = 0x80000000L,
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size = 0x10000000L,
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beatBytes = site(MemoryBusParams).beatBytes,
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idBits = 4)
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case ExtBus => MasterPortParams(
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base = 0x60000000L,
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size = 0x20000000L,
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beatBytes = site(MemoryBusParams).beatBytes,
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idBits = 4)
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case ExtIn => SlavePortParams(beatBytes = 8, idBits = 8, sourceBits = 4)
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// Additional device Parameters
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case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
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case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
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}))
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class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new WithNBigCores(1) ++ new BaseConfig)
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class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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class DualChannelDualBankConfig extends Config(
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
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class Edge128BitConfig extends Config(
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new WithEdgeDataBits(128) ++ new BaseConfig)
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class Edge32BitConfig extends Config(
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new WithEdgeDataBits(32) ++ new BaseConfig)
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class SingleChannelBenchmarkConfig extends Config(new DefaultConfig)
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class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
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class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
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class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
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class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
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class DualCoreConfig extends Config(
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new WithNBigCores(2) ++ new BaseConfig)
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class HeterogeneousDualCoreConfig extends Config(
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new WithNSmallCores(1) ++ new WithNBigCores(1) ++ new BaseConfig)
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class TinyConfig extends Config(
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new WithNMemoryChannels(0) ++
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new WithStatelessBridge ++
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new WithNTinyCores(1) ++
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new BaseConfig)
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class DefaultFPGAConfig extends Config(new BaseConfig)
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class DefaultFPGASmallConfig extends Config(new WithNSmallCores(1) ++ new DefaultFPGAConfig)
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