71 lines
1.8 KiB
Scala
71 lines
1.8 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import junctions.NastiConstants._
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import cde.{Parameters, Field}
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/** Number of tiles */
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case object NTiles extends Field[Int]
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class PRCITileIO(implicit p: Parameters) extends Bundle {
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val reset = Bool(OUTPUT)
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val id = UInt(OUTPUT, log2Up(p(NTiles)))
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val interrupts = new Bundle {
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val mtip = Bool()
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val msip = Bool()
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val meip = Bool()
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val seip = Bool()
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val debug = Bool()
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}.asOutput
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override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
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}
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class PRCI(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val id = UInt(INPUT, log2Up(p(NTiles)))
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val interrupts = new Bundle {
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val mtip = Bool()
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val meip = Bool()
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val seip = Bool()
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val debug = Bool()
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}.asInput
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val tl = new ClientUncachedTileLinkIO().flip
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val tile = new PRCITileIO
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}
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val ipi = Reg(init=Bool(false))
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val acq = Queue(io.tl.acquire, 1)
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val read = acq.bits.isBuiltInType(Acquire.getType)
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val write = acq.bits.isBuiltInType(Acquire.putType)
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val rdata = Wire(init=ipi)
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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val regSize = 16
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val nRegs = 2
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val addr = acq.bits.full_addr()(log2Up(regSize*nRegs)-1,log2Up(regSize))
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when (addr === UInt(0) && write) {
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ipi := acq.bits.data(0)
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}
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io.tile.interrupts := io.interrupts
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io.tile.interrupts.msip := ipi
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io.tile.id := io.id
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}
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