82 lines
2.0 KiB
Verilog
82 lines
2.0 KiB
Verilog
// See LICENSE.SiFive for license details.
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//VCS coverage exclude_file
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import "DPI-C" function int debug_tick
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(
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output bit debug_req_valid,
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input bit debug_req_ready,
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output int debug_req_bits_addr,
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output int debug_req_bits_op,
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output int debug_req_bits_data,
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input bit debug_resp_valid,
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output bit debug_resp_ready,
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input int debug_resp_bits_resp,
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input int debug_resp_bits_data
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);
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module SimDTM(
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input clk,
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input reset,
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output debug_req_valid,
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input debug_req_ready,
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output [ 6:0] debug_req_bits_addr,
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output [ 1:0] debug_req_bits_op,
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output [31:0] debug_req_bits_data,
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input debug_resp_valid,
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output debug_resp_ready,
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input [ 1:0] debug_resp_bits_resp,
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input [31:0] debug_resp_bits_data,
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output [31:0] exit
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);
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bit r_reset;
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wire #0.1 __debug_req_ready = debug_req_ready;
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wire #0.1 __debug_resp_valid = debug_resp_valid;
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wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
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wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
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bit __debug_req_valid;
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int __debug_req_bits_addr;
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int __debug_req_bits_op;
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int __debug_req_bits_data;
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bit __debug_resp_ready;
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int __exit;
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assign #0.1 debug_req_valid = __debug_req_valid;
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assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
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assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
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assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
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assign #0.1 debug_resp_ready = __debug_resp_ready;
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assign #0.1 exit = __exit;
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always @(posedge clk)
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begin
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r_reset <= reset;
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if (reset || r_reset)
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begin
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__debug_req_valid = 0;
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__debug_resp_ready = 0;
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__exit = 0;
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end
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else
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begin
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__exit = debug_tick(
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__debug_req_valid,
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__debug_req_ready,
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__debug_req_bits_addr,
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__debug_req_bits_op,
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__debug_req_bits_data,
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__debug_resp_valid,
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__debug_resp_ready,
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__debug_resp_bits_resp,
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__debug_resp_bits_data
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);
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end
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end
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endmodule
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