#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------

# Verilog sources

sim_vsrcs = \
	$(generated_dir)/$(MODEL).v \
	$(generated_dir)/memdessertMemDessert.v \
	$(base_dir)/vsrc/const.vh \
	$(base_dir)/vsrc/rocketTestHarness.v \
	$(base_dir)/vsrc/bram_mem.v \

# C sources

sim_csrcs = \
	$(base_dir)/csrc/vcs_main.cc \
	$(base_dir)/csrc/mm.cc \
	$(base_dir)/csrc/mm_dramsim2.cc \

#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------

verilog: $(sim_vsrcs)

.PHONY: verilog

#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

VCS = vcs -full64

VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
	+rad +v2k +vcs+lic+wait \
	+vc+list -CC "-I$(VCS_HOME)/include" \
	-CC "-I$(RISCV)/include" \
	-CC "-I$(realpath $(base_dir))/dramsim2" \
	-CC "-std=c++11" \
	-CC "-Wl,-rpath,$(RISCV)/lib" \
	-e vcs_main \
	$(RISCV)/lib/libfesvr.so \
	$(sim_dir)/libdramsim.a \
	+define+TOP=$(MODEL) \
	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
	+define+PRINTF_COND=rocketTestHarness.verbose \
	+libext+.v \

#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------

simv = $(sim_dir)/simv
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
	cd $(sim_dir) && \
	$(VCS) $(VCS_OPTS) -o $(simv) \

simv_debug = $(sim_dir)/simv-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
	cd $(sim_dir) && \
	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
	+define+DEBUG -debug_pp \

#	+define+MEM_BACKUP_EN \

#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------

seed = $(shell date +%s)
exec_simv = $(simv) -q +ntb_random_seed_automatic
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic