package Top {

import Chisel._
import Node._;
import Constants._
import Instructions._

class ioDpathAll extends Bundle()
{
  val host  = new ioHost();
  val ctrl  = new ioCtrlDpath().flip();
  val debug = new ioDebug();
  val dmem  = new ioDmem(List("req_addr", "req_data", "req_tag", "resp_val", "resp_tag", "resp_data")).flip();
  val imem  = new ioImem(List("req_addr", "resp_data")).flip();
}

class rocketDpath extends Component
{
  val io  = new ioDpathAll();
  
  val btb = new rocketDpathBTB(); 
  val if_btb_target = btb.io.target;

  val pcr = new rocketDpathPCR(); 
  val ex_pcr = pcr.io.r.data;

  val alu = new rocketDpathALU(); 
  val ex_alu_out = alu.io.out; 
  val ex_jr_target = ex_alu_out(31,0);

  val div = new rocketDivider(64);
  val div_result = div.io.div_result_bits;
  val div_result_tag = div.io.div_result_tag;
  val div_result_val = div.io.div_result_val;
  
  val mul = new rocketMultiplier();
  val mul_result = mul.io.result; 
  val mul_result_tag = mul.io.result_tag; 
  val mul_result_val = mul.io.result_val;
  
	val rfile = new rocketDpathRegfile();

  // instruction fetch definitions
  val if_reg_pc     = Reg(width = 32, resetVal = UFix(0, 32));

  // instruction decode definitions
  val id_reg_pc        = Reg(resetVal = UFix(0,32));
  val id_reg_pc_plus4  = Reg(resetVal = UFix(0,32));
  val id_reg_inst      = Reg(resetVal = NOP);

  // execute definitions
  val ex_reg_pc             = Reg(resetVal = UFix(0,32));
  val ex_reg_pc_plus4       = Reg(resetVal = UFix(0,32));
  val ex_reg_inst           = Reg(resetVal = Bits(0,32));
  val ex_reg_raddr2         = Reg(resetVal = UFix(0,5));
  val ex_reg_raddr1         = Reg(resetVal = UFix(0,5));
  val ex_reg_rs2            = Reg(resetVal = Bits(0,64));
  val ex_reg_rs1            = Reg(resetVal = Bits(0,64));
  val ex_reg_waddr          = Reg(resetVal = UFix(0,5));
  val ex_reg_ctrl_sel_alu2  = Reg(resetVal = A2_X);
  val ex_reg_ctrl_sel_alu1  = Reg(resetVal = A1_X);
  val ex_reg_ctrl_fn_dw     = Reg(resetVal = DW_X);
  val ex_reg_ctrl_fn_alu    = Reg(resetVal = FN_X);
  val ex_reg_ctrl_ll_wb     = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_mul_val   = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_mul_fn    = Reg(resetVal = MUL_X);
  val ex_reg_ctrl_div_val   = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_div_fn    = Reg(resetVal = DIV_X);
  val ex_reg_ctrl_sel_wb    = Reg(resetVal = WB_X);
  val ex_reg_ctrl_wen       = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_ren_pcr   = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_wen_pcr   = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_eret      = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_exception = Reg(resetVal = Bool(false));
  val ex_reg_ctrl_cause     = Reg(resetVal = UFix(0,5));
 	val ex_wdata						  = Wire() { Bits() }; 	

  val mem_reg_pc            = Reg(resetVal = UFix(0,32));
  val mem_reg_pc_plus4      = Reg(resetVal = UFix(0,32));
  val mem_reg_waddr         = Reg(resetVal = UFix(0,5));
  val mem_reg_wdata         = Reg(resetVal = Bits(0,64));
  val mem_reg_raddr2        = Reg(resetVal = UFix(0,5));
  val mem_reg_ctrl_ll_wb    = Reg(resetVal = Bool(false));
  val mem_reg_ctrl_div_val   = Reg(resetVal = Bool(false));
  val mem_reg_ctrl_mul_val   = Reg(resetVal = Bool(false));
  val mem_reg_ctrl_wen       = Reg(resetVal = Bool(false));
  val mem_reg_ctrl_wen_pcr   = Reg(resetVal = Bool(false));
  val mem_reg_ctrl_exception = Reg(resetVal = Bool(false));
  
  val wb_reg_pc             = Reg(resetVal = UFix(0,32));
  val wb_reg_pc_plus4       = Reg(resetVal = UFix(0,32));
  val wb_reg_waddr          = Reg(resetVal = UFix(0,5));
  val wb_reg_wdata          = Reg(resetVal = Bits(0,64));
  val wb_reg_ctrl_ll_wb     = Reg(resetVal = Bool(false));
  val wb_reg_raddr2         = Reg(resetVal = UFix(0,5));
  val wb_reg_ctrl_div_val   = Reg(resetVal = Bool(false));
  val wb_reg_ctrl_mul_val   = Reg(resetVal = Bool(false));
  val wb_reg_ctrl_wen       = Reg(resetVal = Bool(false));
  val wb_reg_ctrl_wen_pcr   = Reg(resetVal = Bool(false));

  // instruction fetch stage
  val if_pc_plus4 = if_reg_pc + UFix(4, 32);

  val ex_sign_extend = 
    Cat(Fill(52, ex_reg_inst(21)), ex_reg_inst(21,10));
  val ex_sign_extend_split = 
    Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));

  val branch_adder_rhs =
    Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(30,0), UFix(0, 1)),
        Cat(Fill(6, ex_reg_inst(31)), ex_reg_inst(31,7),          UFix(0, 1)));

  val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;

  btb.io.correct_target := ex_branch_target;

  val if_next_pc =
    Mux(io.ctrl.sel_pc === PC_4,   if_pc_plus4,
    Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
    Mux(io.ctrl.sel_pc === PC_EX4, ex_reg_pc_plus4,
    Mux(io.ctrl.sel_pc === PC_BR,  ex_branch_target,
    Mux(io.ctrl.sel_pc === PC_J,   ex_branch_target,
    Mux(io.ctrl.sel_pc === PC_JR,  ex_jr_target.toUFix,
    Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
    Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc, 
        UFix(0, 32)))))))));

  when (!io.host.start){
    if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;
  }  
  when (!io.ctrl.stallf) {
    if_reg_pc <== if_next_pc;
  }

  io.imem.req_addr :=
    Mux(io.ctrl.stallf, if_reg_pc,
        if_next_pc);

  btb.io.current_pc4    := if_pc_plus4;
  btb.io.hit            ^^ io.ctrl.btb_hit;
  btb.io.wen            ^^ io.ctrl.wen_btb;
  btb.io.correct_pc4    := ex_reg_pc_plus4;

  // instruction decode stage
  when (!io.ctrl.stalld) {
    id_reg_pc <== if_reg_pc;
    id_reg_pc_plus4 <== if_pc_plus4; 
    when(io.ctrl.killf) {
      id_reg_inst <== NOP;
    }
    otherwise {
      id_reg_inst <== io.imem.resp_data;
    }
  }

  val id_raddr1 = id_reg_inst(26,22).toUFix;
  val id_raddr2 = id_reg_inst(21,17).toUFix;

	// regfile read
  rfile.io.r0.en   ^^ io.ctrl.ren2;
  rfile.io.r0.addr := id_raddr2;
  val id_rdata2 = rfile.io.r0.data;

  rfile.io.r1.en   ^^ io.ctrl.ren1;
  rfile.io.r1.addr := id_raddr1;
  val id_rdata1 = rfile.io.r1.data;

  // destination register selection
  val id_waddr =
    Mux(io.ctrl.div_wb, div_result_tag,
    Mux(io.ctrl.mul_wb, mul_result_tag,
    Mux(io.ctrl.sel_wa === WA_RD, id_reg_inst(31,27).toUFix,
    Mux(io.ctrl.sel_wa === WA_RA, RA,
        UFix(0, 5)))));

  // bypass muxes
  val id_rs1 =
  	Mux(io.ctrl.div_wb, div_result,
  	Mux(io.ctrl.mul_wb, mul_result,
    Mux(id_raddr1 != UFix(0, 5) && ex_reg_ctrl_wen  && id_raddr1 === ex_reg_waddr,  ex_wdata,
    Mux(id_raddr1 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
    Mux(id_raddr1 != UFix(0, 5) && wb_reg_ctrl_wen  && id_raddr1 === wb_reg_waddr,  wb_reg_wdata,
        id_rdata1)))));

  val id_rs2 =
    Mux(id_raddr2 != UFix(0, 5) && ex_reg_ctrl_wen  && id_raddr2 === ex_reg_waddr,  ex_wdata,
    Mux(id_raddr2 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
    Mux(id_raddr2 != UFix(0, 5) && wb_reg_ctrl_wen  && id_raddr2 === wb_reg_waddr,  wb_reg_wdata,
        id_rdata2)));
        
  // write value to cause register based on exception type
	val id_exception = io.ctrl.xcpt_illegal || io.ctrl.xcpt_privileged || io.ctrl.xcpt_fpu || io.ctrl.xcpt_syscall;
	val id_cause = 
		Mux(io.ctrl.xcpt_illegal, UFix(2,5),
		Mux(io.ctrl.xcpt_privileged, UFix(3,5),
		Mux(io.ctrl.xcpt_fpu, UFix(4,5),
		Mux(io.ctrl.xcpt_syscall, UFix(6,5), 
			UFix(0,5)))));

  io.ctrl.inst := id_reg_inst;
//   io.ctrl.rs1  := id_rs1;
//   io.ctrl.rs2  := id_rs2;

  // execute stage
  ex_reg_pc             <== id_reg_pc;
  ex_reg_pc_plus4       <== id_reg_pc_plus4;
  ex_reg_inst           <== id_reg_inst;
  ex_reg_raddr2         <== id_raddr2;
  ex_reg_raddr1         <== id_raddr1;
  ex_reg_rs2            <== id_rs2;
  ex_reg_rs1            <== id_rs1;
  ex_reg_waddr          <== id_waddr;
  ex_reg_ctrl_sel_alu2  <== io.ctrl.sel_alu2;
  ex_reg_ctrl_sel_alu1  <== io.ctrl.sel_alu1.toUFix;
  ex_reg_ctrl_fn_dw     <== io.ctrl.fn_dw.toUFix;
  ex_reg_ctrl_fn_alu    <== io.ctrl.fn_alu;
  ex_reg_ctrl_mul_fn    <== io.ctrl.mul_fn;
  ex_reg_ctrl_div_fn    <== io.ctrl.div_fn;
  ex_reg_ctrl_ll_wb     <== io.ctrl.div_wb | io.ctrl.mul_wb; // TODO: verify
  ex_reg_ctrl_sel_wb    <== io.ctrl.sel_wb;
  ex_reg_ctrl_ren_pcr   <== io.ctrl.ren_pcr;
  ex_reg_ctrl_cause     <== id_cause;

  when(io.ctrl.killd) {
    ex_reg_ctrl_div_val 	<== Bool(false);
    ex_reg_ctrl_mul_val   <== Bool(false);
    ex_reg_ctrl_wen     	<== Bool(false);
    ex_reg_ctrl_wen_pcr 	<== Bool(false);
    ex_reg_ctrl_eret			<== Bool(false);
  	ex_reg_ctrl_exception <== Bool(false);
  } 
  otherwise {
    ex_reg_ctrl_div_val 	<== io.ctrl.div_val;
  	ex_reg_ctrl_mul_val   <== io.ctrl.mul_val;
    ex_reg_ctrl_wen     	<== io.ctrl.wen;
    ex_reg_ctrl_wen_pcr		<== io.ctrl.wen_pcr;
    ex_reg_ctrl_eret			<== io.ctrl.eret;
    ex_reg_ctrl_exception <== id_exception;
  }

  val ex_alu_in2 =
    Mux(ex_reg_ctrl_sel_alu2 === A2_0,     UFix(0, 64),
    Mux(ex_reg_ctrl_sel_alu2 === A2_SEXT,  ex_sign_extend,
    Mux(ex_reg_ctrl_sel_alu2 === A2_SPLIT, ex_sign_extend_split,
    Mux(ex_reg_ctrl_sel_alu2 === A2_RS2,   ex_reg_rs2,
        UFix(0, 64)))));

  val ex_alu_in1 =
    Mux(ex_reg_ctrl_sel_alu1 === A1_RS1, ex_reg_rs1,
    Mux(ex_reg_ctrl_sel_alu1 === A1_LUI, Cat(Fill(32, ex_reg_inst(26)),ex_reg_inst(26,7),UFix(0, 12)),
        UFix(0, 64)));

  val ex_alu_shamt =
    Cat(ex_alu_in2(5) & ex_reg_ctrl_fn_dw === DW_64, ex_alu_in2(4,0)).toUFix;

  alu.io.dw    := ex_reg_ctrl_fn_dw;
  alu.io.fn    := ex_reg_ctrl_fn_alu;
  alu.io.shamt := ex_alu_shamt.toUFix;
  alu.io.in2   := ex_alu_in2.toUFix;
  alu.io.in1   := ex_alu_in1.toUFix;
  
  // divider
  div.io.div_fn    := ex_reg_ctrl_div_fn;
  div.io.div_val   := ex_reg_ctrl_div_val;
  div.io.div_waddr := ex_reg_waddr;
  div.io.dpath_rs1 := ex_reg_rs1;
  div.io.dpath_rs2 := ex_reg_rs2;
  div.io.div_result_rdy := io.ctrl.div_wb;
  
  io.ctrl.div_rdy 				:= div.io.div_rdy;
  io.ctrl.div_result_val := div.io.div_result_val;
  
  // multiplier
  mul.io.mul_val := ex_reg_ctrl_mul_val;
  mul.io.mul_fn	 := ex_reg_ctrl_mul_fn;
  mul.io.mul_tag := ex_reg_waddr;
  mul.io.in0		 := ex_reg_rs1;
  mul.io.in1		 := ex_reg_rs2;
  
  io.ctrl.mul_result_val := mul.io.result_val;
  
  io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection

  // D$ request interface (registered inside D$ module)
  // other signals (req_val, req_rdy) connect to control module  
  io.dmem.req_addr  := ex_alu_out;
  io.dmem.req_data  := ex_reg_rs2;
  io.dmem.req_tag   := ex_reg_waddr;

	// processor control regfile read
  pcr.io.r.en   := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_exception | ex_reg_ctrl_eret;
  pcr.io.r.addr := 
  	Mux(ex_reg_ctrl_exception, PCR_EVEC, 
  	Mux(ex_reg_ctrl_eret, PCR_EPC, 
  		ex_reg_raddr2));
  		
  pcr.io.host.from_wen ^^ io.host.from_wen;
  pcr.io.host.from     ^^ io.host.from;
  pcr.io.host.to       ^^ io.host.to;

  pcr.io.eret      	:= ex_reg_ctrl_eret;
  pcr.io.exception 	:= ex_reg_ctrl_exception;
  pcr.io.cause 			:= ex_reg_ctrl_cause;
  pcr.io.pc					:= ex_reg_pc;
  
  io.ctrl.status   := pcr.io.status;
 	io.debug.error_mode  := pcr.io.debug.error_mode;
 	io.debug.log_control := pcr.io.debug.log_control;
  
	// branch resolution logic
  io.ctrl.br_eq   := (ex_reg_rs1 === ex_reg_rs2);
  io.ctrl.br_ltu  := (ex_reg_rs1.toUFix < ex_reg_rs2.toUFix);
  io.ctrl.br_lt :=
    (~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
    ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;

	// writeback select mux
  ex_wdata :=
    Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
    Mux(ex_reg_ctrl_sel_wb === WB_PC,  ex_reg_pc_plus4,
    Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
    Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
        Bits(0, 64))))).toBits;
        
  // memory stage
  mem_reg_pc                <== ex_reg_pc;
  mem_reg_pc_plus4          <== ex_reg_pc_plus4;
  mem_reg_waddr             <== ex_reg_waddr;
  mem_reg_wdata             <== ex_wdata;
  mem_reg_ctrl_ll_wb        <== ex_reg_ctrl_ll_wb;
  mem_reg_raddr2            <== ex_reg_raddr2;

  when (io.ctrl.killx) {
    mem_reg_ctrl_div_val   <== Bool(false);
    mem_reg_ctrl_mul_val   <== Bool(false);
    mem_reg_ctrl_wen     	 <== Bool(false);
    mem_reg_ctrl_wen_pcr 	 <== Bool(false);
    mem_reg_ctrl_exception <== Bool(false);
  }
  otherwise {
    mem_reg_ctrl_div_val   <== ex_reg_ctrl_div_val;
    mem_reg_ctrl_mul_val   <== ex_reg_ctrl_mul_val;
    mem_reg_ctrl_wen     	 <== ex_reg_ctrl_wen;
    mem_reg_ctrl_wen_pcr 	 <== ex_reg_ctrl_wen_pcr;
    mem_reg_ctrl_exception <== ex_reg_ctrl_exception;
  }
  
  // exception signal to control (for NPC select)
  io.ctrl.exception := mem_reg_ctrl_exception;
  
  // writeback stage
  val r_dmem_resp_val      = Reg(io.dmem.resp_val);
  val r_dmem_resp_waddr    = Reg(io.dmem.resp_tag(4,0).toUFix);
  val r_dmem_resp_pos      = Reg(io.dmem.resp_tag(7,5));
  val r_dmem_resp_type     = Reg(io.dmem.resp_tag(9,8));
  val r_dmem_resp_data     = Reg(io.dmem.resp_data);

  wb_reg_pc           <== mem_reg_pc;
  wb_reg_pc_plus4     <== mem_reg_pc_plus4;
  wb_reg_waddr        <== mem_reg_waddr;
  wb_reg_wdata        <== mem_reg_wdata;
  wb_reg_ctrl_ll_wb   <== mem_reg_ctrl_ll_wb;
  wb_reg_raddr2       <== mem_reg_raddr2;

  when (io.ctrl.killm) {
    wb_reg_ctrl_div_val   <== Bool(false);
    wb_reg_ctrl_mul_val   <== Bool(false);
    wb_reg_ctrl_wen       <== Bool(false);
    wb_reg_ctrl_wen_pcr 	<== Bool(false);
  }
  otherwise {
    wb_reg_ctrl_div_val   <== mem_reg_ctrl_div_val;
    wb_reg_ctrl_mul_val   <== mem_reg_ctrl_mul_val;
    wb_reg_ctrl_wen     	<== mem_reg_ctrl_wen;
    wb_reg_ctrl_wen_pcr 	<== mem_reg_ctrl_wen_pcr;
  }

  // crossbar/sign extension for 8/16/32 bit loads
  val dmem_resp_data_w = 
    Mux(r_dmem_resp_pos(2).toBool, r_dmem_resp_data(63, 32), r_dmem_resp_data(31, 0));
  val dmem_resp_data_h = 
    Mux(r_dmem_resp_pos(1).toBool, dmem_resp_data_w(31, 16),  dmem_resp_data_w(15, 0));
  val dmem_resp_data_b = 
    Mux(r_dmem_resp_pos(0).toBool, dmem_resp_data_h(15, 8),   dmem_resp_data_h(7, 0));

  val dmem_resp_data_final =
    Mux(r_dmem_resp_type === MT_B,  Cat(Fill(56, dmem_resp_data_b(7)), dmem_resp_data_b),
    Mux(r_dmem_resp_type === MT_BU, Cat(UFix(0, 56), dmem_resp_data_b),
    Mux(r_dmem_resp_type === MT_H,  Cat(Fill(48, dmem_resp_data_h(15)), dmem_resp_data_h),
    Mux(r_dmem_resp_type === MT_HU, Cat(UFix(0, 48), dmem_resp_data_h),
    Mux(r_dmem_resp_type === MT_W,  Cat(Fill(32, dmem_resp_data_w(31)), dmem_resp_data_w),
    Mux(r_dmem_resp_type === MT_WU, Cat(UFix(0, 32), dmem_resp_data_w),
    Mux(r_dmem_resp_type === MT_D,  r_dmem_resp_data,
        UFix(0, 64))))))));

	// regfile write
  rfile.io.w0.addr := wb_reg_waddr;
  rfile.io.w0.en   := wb_reg_ctrl_wen | wb_reg_ctrl_ll_wb;
  rfile.io.w0.data := wb_reg_wdata; 
  
  rfile.io.w1.addr := r_dmem_resp_waddr;
  rfile.io.w1.en   := r_dmem_resp_val;
  rfile.io.w1.data := dmem_resp_data_final;
  
  // scoreboard set (for D$ misses, div, mul)
  io.ctrl.sboard_set    := wb_reg_ctrl_div_val | wb_reg_ctrl_mul_val | io.ctrl.dcache_miss;
  io.ctrl.sboard_seta   := wb_reg_waddr;
  
  // scoreboard clear (for div/mul and D$ load miss writebacks)
  io.ctrl.sboard_clr0   := wb_reg_ctrl_ll_wb;
  io.ctrl.sboard_clr0a  := wb_reg_waddr;
  io.ctrl.sboard_clr1   := r_dmem_resp_val;
  io.ctrl.sboard_clr1a  := r_dmem_resp_waddr;  

	// processor control regfile write
  pcr.io.w.addr := wb_reg_raddr2;
  pcr.io.w.en   := wb_reg_ctrl_wen_pcr;
  pcr.io.w.data := wb_reg_wdata;

}

}