riscv/rocket-chip
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1337 Commits

Author SHA1 Message Date
Andrew Waterman
4c8be13a4d Improve homogeneity circuit QoR 2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132 mideleg/medeleg not present without less-privileged traps 2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5 Share PMP mask gen between I$ and D$ 2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf More WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422 Flush pipeline from WB stage, not MEM 
Fixes sptbr write -> instruction translation hazard.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab Retime PTW response valid bits 
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316 Get TLB permission checks off D$ clock gating critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4 Expose MXR to S-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman
2a413e4496 Remove fruitless debug() 2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23 Simplify interrupt-stack discipline 
f2ed45b179
 2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2 Mitigate some more PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3 Don't gate exception-cause pipeline registers separately 
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
 2017-03-24 16:39:52 -07:00
Andrew Waterman
3ea822c2cf Make blocking L1 D$ the default 
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
487b8db5ef Address some PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman
03fb334c4c Take mprv calculation off critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman
f0796f0509 Pass correct access size information to PMP checker 2017-03-24 16:39:52 -07:00
Andrew Waterman
a6874c03f7 Remove DecoupledTLB 2017-03-24 16:39:52 -07:00
Andrew Waterman
78f9f6b9ef When SFENCE.VMA has rs2 != x0, don't flush global mappings 2017-03-24 16:39:52 -07:00
Andrew Waterman
1b950128e1 PTW should always use S-mode privilege 
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode.  However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.

Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857 WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
b1b405404d Set PRV=M when entering debug mode 
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
cf168e419b Support SFENCE.VMA rs1 argument 
This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
 2017-03-24 16:39:52 -07:00
Henry Cook
797c18b8db Make some requirement failures more verbose (#608) 
* tilelink: verbose requires in xbar

* diplomacy: verbose requires
 2017-03-23 21:55:11 -07:00
Wesley W. Terpstra
bd08f10816 tilelink2: make sink ids optional (#607) 
* tilelink2: make sink ids optional

* CacheCork: add a special-case for 1 sink id
 2017-03-23 18:19:04 -07:00
Wesley W. Terpstra
19eb9b6906 l1tol2: put a flow Q on the exits (#606) 
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
 2017-03-23 16:28:32 -07:00
Henry Cook
055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) 2017-03-22 14:38:33 -07:00
Andrew Waterman
76f083b469 FIFOFixer: Not all D-channel messages are A-channel responses 2017-03-21 14:17:38 -07:00
Andrew Waterman
3609254e4a There's no structural hazard on MMIO store responses 
So don't stall as though there were.
 2017-03-21 14:17:32 -07:00
Yunsup Lee
5eae7e1da4 make DCache s1_nack less conservative for pipelined MMIO requests 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4c00066746 rocket: describe dcache as two clients (fifo+cached) 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
81d717e82f coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
198afddb4b tilelink2: add the FIFOFixer 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
930438adba tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
fd521c56a6 tilelink2: add client-side FIFO parameterization 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4eef317e84 RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
04892fea01 Monitor: support early ack 2017-03-20 14:49:19 -07:00
Wesley W. Terpstra
278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
778e189bba Monitor: ProbeAckData and ReleaseData may carry an error 2017-03-20 11:44:13 -07:00
Wesley W. Terpstra
48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Wesley W. Terpstra
c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
a4ca424a22 AHBToTL: finally get the error signal right? (#594) 2017-03-18 22:24:20 -07:00
Wesley W. Terpstra
f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) 2017-03-17 19:34:40 -07:00
Megan Wachs
dcc9827ab4 Rename Prci.scala to Clint.scala (#591) 
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
 2017-03-17 15:36:10 -07:00
Wesley W. Terpstra
db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
9b5b3279a6 AHBToTL: don't report error during idle cycles 2017-03-16 18:18:29 -07:00
Wesley W. Terpstra
5efd38bf97 apb: put both aFlow options under regression 2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33 axi4: use common BufferParams 2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094 unittest: try both aFlow settings of TLToAHB 2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
c95c2ca9c8 AHB: include bridge unit tests 2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089 ahb: implement a ToTL bridge 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925 apb: better test coverage 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5 axi4: improve test harness 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1 tilelink2: optimize the supportsX check circuits 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409 tilelink2: make TLBuffer API more flexible 2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing 
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
 2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c Merge branch 'master' into priv-1.10 2017-03-13 21:40:12 -07:00
Leway Colin
1322a02637 Fixed Hasti can't handle N masters to one slave #571 (#576) 2017-03-13 20:36:53 -07:00
Andrew Waterman
d6f571cbbb Implement mstatus.TSR 2017-03-13 14:50:06 -07:00
Andrew Waterman
1fea0460ba Support superpage entries in TLB 2017-03-13 14:50:06 -07:00
Andrew Waterman
2d267b4940 Support corner cases in TLBPermissions 
Don't crap out if the yes-set or no-set is empty.
 2017-03-13 14:50:06 -07:00
Andrew Waterman
90b5cc96cb Gracefully handle empty ports in AddressDecoder 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
c847559853 TLB: add a helper API to determine homogeneous page permissions 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
eaf474a081 LFSR: use random intial value of the start register 
We just need to make sure it doesn't initialize randomly stuck at 0.
 2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0 Merge branch 'master' into priv-1.10 2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd Zap conflicting TLB entries, preparing for superpage support 
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation.  This
isn't compatible with the Mux1H approach.  So, flush the TLB and report
a miss on duplicate entries.
 2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb Don't double-count release traffic in perfctrs 2017-03-09 16:49:02 -08:00
Andrew Waterman
63f8ce36f6 Avoid VM exceptions in groundtest by setting Accessed bit 2017-03-09 16:48:28 -08:00
Andrew Waterman
4f8f05d635 Add performance counter facility 2017-03-09 13:58:50 -08:00
Andrew Waterman
33b6d48376 Fix haltnot reporting (previously always returned 0) 2017-03-09 13:58:40 -08:00
Andrew Waterman
24a2278fc4 Perform all illegal-instruction detection in ID stage 
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
 2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741 Support unrolling the integer divider 2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf Improve BTB critical path at slight accuracy cost 
Make entries fully associative on lower 14 bits only, not full address.
 2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines 
It's redundant with the new scheme, so just adds HW for no reason.
 2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result 
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
 2017-03-07 20:51:32 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Wesley W. Terpstra
676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
0178248551 diplomacy: evaluate ResourceBindings only once 2017-03-03 02:04:17 -08:00
Wesley W. Terpstra
8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
7660be039c rocketchip: add WithTimebase to set RTC frequency 2017-03-03 00:47:50 -08:00
Wesley W. Terpstra
57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
Wesley W. Terpstra
4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
e322692d16 diplomacy: add DeviceTree renderer 2017-03-02 21:19:14 -08:00
Wesley W. Terpstra
c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet 2017-03-02 11:14:28 -08:00
Wesley W. Terpstra
bb70b1a3c3 diplomacy: add resource tracking 2017-03-02 11:14:28 -08:00
Henry Cook
9bfcb40cb4 util: Majority on sets of bools 2017-02-27 20:18:28 -08:00
Henry Cook
6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments 2017-02-27 19:40:55 -08:00
Henry Cook
62f5727bc6 periphery: peripheryBusBytes and socBusBytes 2017-02-27 19:19:41 -08:00
Andrew Waterman
dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Henry Cook
35877e6ec1 Merge branch 'master' into periphery-adjustments 2017-02-24 10:37:41 -08:00
Leway Colin
87d909e996 Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) 2017-02-24 10:37:26 -08:00
Henry Cook
a281ad8ad2 rocketchip: rename some periphery ports 2017-02-23 18:28:04 -08:00
Henry Cook
6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] 2017-02-23 18:27:44 -08:00
Wesley W. Terpstra
c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Henry Cook
027d6247b6 diplomacy: silence a warning (#560) 2017-02-22 11:28:04 -08:00
Wesley W. Terpstra
9153a9a733 ClockDivider: add docs to appease the reviewer 
... even though this means a delay of 1:30 hours :(
 2017-02-17 19:35:08 +01:00
Wesley W. Terpstra
3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Wesley W. Terpstra
5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) 
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
 2017-02-17 14:26:23 +01:00
Wesley W. Terpstra
924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
bb334a2cf5 util: add fast2slow direction option to rational crossings 
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
 2017-02-17 13:59:51 +01:00
Wesley W. Terpstra
e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. Terpstra
abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Jacob Chang
5fc44bbcda Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554) 2017-02-10 10:19:22 -08:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Jim Lawson
307e0ca9c0 Fix up Absolute value. 
As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt.
 2017-02-08 15:00:43 -08:00
Wesley W. Terpstra
69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) 2017-02-04 15:59:50 -08:00
Wesley W. Terpstra
d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra
a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
Wesley W. Terpstra
b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip 
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
 2017-02-03 17:19:21 -08:00
Wesley W. Terpstra
fc9ea62d38 HeterogeneousBag: a handy container for differently parameterized bundles 2017-02-03 16:21:33 -08:00
Wesley W. Terpstra
7afe383db3 Ecc: detect uncorrectable errors also for SEC 2017-02-03 16:21:09 -08:00
Wesley W. Terpstra
7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
Wesley W. Terpstra
93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Jacob Chang
83a83c778a Added range function in IdRange 
Added source accessor function in TLEdge
 2017-02-02 12:35:57 -08:00
Andrew Waterman
8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN 
See https://github.com/riscv/riscv-isa-sim/issues/76
 2017-02-02 11:55:08 -08:00
Andrew Waterman
75edf42323 Set xPIE=1 on xRET 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
 2017-02-02 11:55:08 -08:00