Wesley W. Terpstra
f6f40b1442
unit tests: all should accept timeout override
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
3e2b477c0a
rational: adjust comments and add a case for N:M
2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
4f0ae1eab7
tilelink2: annotate which test generates RAMModel output
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
5045696f92
TLRational: test all corners
...
In order to ensure that verilator is happy, we launch both clocks from a
clock divider. Sadly, it does not follow the spec wrt. derived clocks.
See the verilator manual section on "Generated Clocks".
2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
924afebbd9
tilelink2: make TLRational have configurable direction
2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
830d01329d
RationalCrossing: add some documentation
2017-01-26 21:27:34 -08:00
Wesley W. Terpstra
fc3b72084f
tilelink2: add a rational clock crossing adapter
2017-01-26 20:07:28 -08:00