2 Commits

Author	SHA1	Message	Date
Jacob Chang	dcda98dcaf	Disable coverage collection for testbench related verilog files (#1204)	2018-01-22 16:40:38 -08:00
Megan Wachs	e82328336e	Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. ... This is simpler than JTAGVPI and is supported better by Verilor. It is also the same thing Spike uses.	2018-01-05 16:02:52 -08:00