537274b645
coreplex: move buffers inside the coreplex
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This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
19485a9861
Merge pull request #609 from ucb-bar/dtb-rom
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DTB in the bootrom
2017-03-24 21:54:13 -07:00
e74226564c
travis: add dependency on device-tree-compiler
2017-03-24 20:59:33 -07:00
f36b1766f8
TLROM: use the smallest ROM implementation that works
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The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
3f0d2fe826
Instantiate PTW unconditionally
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This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
0182b6ca07
bump tools
2017-03-24 16:39:52 -07:00
e9cadf29d2
Improve DCache MMIO QoR
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No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
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This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
3951e57789
Force each TLB entry into its own clock-gate group
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This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
d3bda9574c
Put page homogeneity checker in PMP
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Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
9e05200e51
Don't require that PMP ranges be aligned to access size
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e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
2888779422
Flush pipeline from WB stage, not MEM
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Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
44ca3b60ab
Retime PTW response valid bits
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It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
a03556220c
Default TLB size = 32
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@davidbiancolin
2017-03-24 16:39:52 -07:00
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
2a413e4496
Remove fruitless debug()
2017-03-24 16:39:52 -07:00
29414f3a23
Simplify interrupt-stack discipline
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https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542
2017-03-24 16:39:52 -07:00
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
7484f27ed3
Don't gate exception-cause pipeline registers separately
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They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
3ea822c2cf
Make blocking L1 D$ the default
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The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
1b950128e1
PTW should always use S-mode privilege
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If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
b1b405404d
Set PRV=M when entering debug mode
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Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
cf168e419b
Support SFENCE.VMA rs1 argument
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This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
797c18b8db
Make some requirement failures more verbose ( #608 )
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* tilelink: verbose requires in xbar
* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
bd08f10816
tilelink2: make sink ids optional ( #607 )
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* tilelink2: make sink ids optional
* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
Wesley W. Terpstra
Yunsup Lee
Henry Cook
Andrew Waterman