3 Commits

Author	SHA1	Message	Date
Andrew Waterman	a0dcd42e80	avoid erroneously setting tags valid during flush	2016-09-07 00:05:38 -07:00
Andrew Waterman	63679bb019	Add support for L1 data scratchpads instead of caches ... They fit in the same part of the address space as DRAM would be, and are coherent (because they are not cacheable). They are currently limited to single cores without DRAM. We intend to lift both restrictions, probably when we add support for heterogeneous tiles.	2016-09-02 16:22:07 -07:00
Howard Mao	7b20609d4d	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00