rocket-chip

riscv/rocket-chip

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Commit Graph

Author	SHA1	Message	Date
Henry Cook	c457c9cb9f	tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 16:43:06 -07:00
Wesley W. Terpstra	68ed055f6d	chiplink: adjust bus view to include the splitter (#886 )	2017-07-24 21:41:17 -07:00
Henry Cook	01ca3efc2b	Combine Coreplex and System Module Hierarchies (#875 ) * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless := and := * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC	2017-07-23 08:31:04 -07:00

Author

SHA1

Message

Date

Henry Cook

c457c9cb9f

tilelink: allow insertion of TLDelayer on TLBus outward node

2017-08-07 16:43:06 -07:00

Wesley W. Terpstra

68ed055f6d

chiplink: adjust bus view to include the splitter (#886 )

2017-07-24 21:41:17 -07:00

Henry Cook

01ca3efc2b

Combine Coreplex and System Module Hierarchies (#875 )

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

2017-07-23 08:31:04 -07:00

3 Commits