* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.