Howard Mao
18ffe7b1ec
don't use +verbose in vsim .run rule
2016-05-04 23:01:14 -07:00
Andrew Waterman
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Howard Mao
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
Howard Mao
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
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This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
Palmer Dabbelt
cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Christopher Celio
83df4bcc35
Fixed run-bmark-tests make target in vsim
2015-09-09 22:37:47 -07:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
