9 Commits

Author	SHA1	Message	Date
Henry Cook	dae6772624	factor out common cache subcomponents into uncore.util	2016-11-23 12:09:35 -08:00
Wesley W. Terpstra	c18bc07bbc	TLB: determine RWX from TL2 properties directly	2016-11-21 21:13:26 -08:00
Wesley W. Terpstra	37a3c22639	rocketchip: move from using cde to config	2016-11-18 16:18:33 -08:00
Wesley W. Terpstra	30425d1665	rocketchip: eliminate all Knobs	2016-11-18 14:31:42 -08:00
Andrew Waterman	eddf1679f5	Use <> instead of := for bi-directional connections	2016-10-04 22:29:39 -07:00
Howard Mao	ab3219cf6e	don't use Scala to Chisel implicit conversions outside of rocket	2016-09-29 14:35:42 -07:00
Howard Mao	9910c69c67	Move a bunch more things into util package ... A lot of utility code was just being imported willy-nilly from one package to another. This moves the common code into util to make things more sensible. The code moved were * The AsyncQueue and AsyncDecoupledCrossing from junctions. * All of the code in rocket's util.scala * The BlackBox asynchronous reset registers from uncore.tilelink2 * The implicit definitions from uncore.util	2016-09-29 14:23:42 -07:00
Howard Mao	403cc1c5c4	fix DecoupledTLB to handle misses appropriately	2016-08-31 22:00:27 -07:00
Howard Mao	7b20609d4d	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00