Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
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This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
Wesley W. Terpstra
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
Wesley W. Terpstra
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
Wesley W. Terpstra
dcb9383568
PositionalMultiQueue: work around vcs Lint report
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Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
may need to be inout. Coercing to inout.
2016-10-10 11:21:49 -07:00
Wesley W. Terpstra
5d905a5310
PositionalMultiQueue: shared storage FIFO 1-push n-pop
2016-10-10 11:21:49 -07:00