Wesley W. Terpstra
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7c334e3c34
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axi4 ToTL: shorter critical path on Q.bits if errors go first
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2016-10-17 01:00:49 -07:00 |
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Wesley W. Terpstra
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73010c79a3
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axi4 ToTL: handle bad AXI addresses
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2016-10-17 00:12:26 -07:00 |
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Wesley W. Terpstra
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501d6d689f
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axi4: Test ToTL
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2016-10-16 22:04:06 -07:00 |
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Wesley W. Terpstra
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5a1da63b5a
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axi4: prototype ToTL adapter
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2016-10-16 22:04:01 -07:00 |
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Wesley W. Terpstra
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72e5a97d40
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tilelink2: factor out the OH1ToOH function
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2016-10-16 22:04:01 -07:00 |
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Wesley W. Terpstra
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d09f43c32f
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axi4 Bundles: add a size calculation helper
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
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2016-10-16 22:04:01 -07:00 |
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Wesley W. Terpstra
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4c1c52486b
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axi4 Fragmenter: handle more inflight AXI requests than we have space
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2016-10-13 15:52:32 -07:00 |
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Wesley W. Terpstra
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8005266131
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axi4 Fragmenter: refine sideband FSM for case of last fragment
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2016-10-13 15:52:32 -07:00 |
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Wesley W. Terpstra
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19064e602b
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axi4 Fragmenter: align all output accesses
We promised the output is aligned. Make good on that!
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2016-10-13 15:52:27 -07:00 |
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Wesley W. Terpstra
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84be93f9f3
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axi4 Fragmenter: confirm correct handling of last
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2016-10-13 14:01:23 -07:00 |
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Wesley W. Terpstra
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1c79a23a8b
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axi4 Fragmenter: initialize error response to 0
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2016-10-13 13:46:24 -07:00 |
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Wesley W. Terpstra
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958af132ba
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axi4 Fragmenter: optimize dynamic slave lookup
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2016-10-12 17:29:38 -07:00 |
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Wesley W. Terpstra
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11169d155c
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axi4: add a Buffer to put between nodes
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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a9a3f7dd4e
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tilelink2 RAMModel: include name of test in output
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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345eefd81b
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axi4: include unit tests
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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a6c6d99848
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axi4: prototype Fragmenter
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2016-10-12 17:08:49 -07:00 |
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Wesley W. Terpstra
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c918aa6d89
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axi4: name AdapterNode parameters properly
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2016-10-12 17:02:02 -07:00 |
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Wesley W. Terpstra
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a423f97844
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axi4: parameterized AXI master constraint for aligned access
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2016-10-12 17:02:02 -07:00 |
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Wesley W. Terpstra
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38b6c1c820
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tilelink2 axi4: RegisterRouter can cut ready dependency
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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dc26736f32
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axi4 tilelink2: include minAlignment and maxAddress in slaves
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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876609eb0e
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diplomacy: add NodeHandles to support abstraction
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2016-10-10 13:15:25 -07:00 |
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Wesley W. Terpstra
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e856cbe3a6
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axi4: SRAM for testing
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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abb02aa6f4
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axi4: add a RegisterRouter for generic devices
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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b29d34038e
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axi4: diplomacy capable AXI4
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2016-10-10 11:21:50 -07:00 |
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