riscv/rocket-chip
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3 Commits

Author SHA1 Message Date
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00