6 Commits

Author	SHA1	Message	Date
Henry Cook	4c595d175c	Refactor package hierarchy and remove legacy bus protocol implementations (#845) ... * Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package	2017-07-07 10:48:16 -07:00
Wesley W. Terpstra	2119df5a60	vsrc: add ClockDivider3 used to simulate unaligned clocks	2017-05-14 15:05:55 -07:00
Wesley W. Terpstra	9153a9a733	ClockDivider: add docs to appease the reviewer ... ... even though this means a delay of 1:30 hours :(	2017-02-17 19:35:08 +01:00
Wesley W. Terpstra	91d1880dbf	ClockDivider2: fix launch alignment of clocks (vcs) ... Doing this in Chisel leads to non-determinism due to shitty Verilog ordering semantis. Using an '=' ensures that all of the clock posedges fire before concurrent register updates. See "Gotcha 29: Sequential logic that requires blocking assignments" in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.	2017-02-17 14:26:23 +01:00
Wesley W. Terpstra	b7963eca4e	copyright: ran scripts/modify-copyright	2016-11-27 22:15:43 -08:00
Howard Mao	cd96a66ba6	replace verilog clock divider with one written in Chisel	2016-09-22 11:32:29 -07:00