2 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	4f0ae1eab7	tilelink2: annotate which test generates RAMModel output	2017-04-14 15:13:40 -07:00
Wesley W. Terpstra	6fc3ec3d63	tileink2: add a TestRAM; a zero-delay RAM useful for testing ... TLRAM always answers after 1 cycle. We need a RAM that answers in 0.	2017-03-14 14:06:17 -07:00