rocket-chip

riscv/rocket-chip

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Commit Graph

Author	SHA1	Message	Date
Wesley W. Terpstra	9153a9a733	ClockDivider: add docs to appease the reviewer ... even though this means a delay of 1:30 hours :(	2017-02-17 19:35:08 +01:00
Wesley W. Terpstra	91d1880dbf	ClockDivider2: fix launch alignment of clocks (vcs) Doing this in Chisel leads to non-determinism due to shitty Verilog ordering semantis. Using an '=' ensures that all of the clock posedges fire before concurrent register updates. See "Gotcha 29: Sequential logic that requires blocking assignments" in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.	2017-02-17 14:26:23 +01:00

Author

SHA1

Message

Date

Wesley W. Terpstra

9153a9a733

ClockDivider: add docs to appease the reviewer

... even though this means a delay of 1:30 hours :(

2017-02-17 19:35:08 +01:00

Wesley W. Terpstra

91d1880dbf

ClockDivider2: fix launch alignment of clocks (vcs)

Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.

2017-02-17 14:26:23 +01:00

2 Commits