Yunsup Lee
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
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This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
Yunsup Lee
b76612f357
relax contraint on adding AddrMapEntry to AddrMap ( #248 )
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now you can add them in any order. there's an explicit check at the end to figure out whether there are overlapping regions.
2016-09-06 21:53:55 -07:00
Howard Mao
66de89c4db
allow fixed priority routing in Junctions arbiters
2016-09-04 10:55:19 -07:00
Howard Mao
efe8670283
allow Serializer/Deserializer to work with arbitrary Chisel data types
2016-09-04 10:55:19 -07:00
Howard Mao
b9b79e4fb6
get rid of AtoS RTL
2016-09-04 10:55:19 -07:00
Yunsup Lee
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
Megan Wachs
75efc7dee7
JtagIO's DRV_TDO should be an INPUT
2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb
Move files after the file reorganization
2016-08-19 16:11:41 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
