4 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	606f19a17f	tilelink2: RegisterRouter Unit Test	2016-09-12 22:13:39 -07:00
Wesley W. Terpstra	85ae77c108	tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible	2016-09-12 10:32:25 -07:00
Wesley W. Terpstra	98a4facac7	tilelink2 RAMModel: clear Mems on power-up	2016-09-12 10:32:24 -07:00
Wesley W. Terpstra	17f7ab18de	tilelink2 RAMModel: model the state a RAM would have for Put+Gets	2016-09-12 10:32:24 -07:00