rocket-chip

riscv/rocket-chip

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Author	SHA1	Message	Date
Megan Wachs	f86489b59e	JTAG: Use sorted map for stability (#1073 ) * JTAG: Use sorted map for stability Otherwise the generated FIRRTL/Verilog is non deterministic * jtag : parens for clarity * jtag: Use deterministic ListMap and sort for stability * JTAG: use slightly clearer SortedMap (clearer to me anyway) * jtag: whitespace cleanup	2017-10-31 15:33:41 -07:00
Henry Cook	b86f4b9bb7	config: use Field defaults over Config defaults Also rename some keys that had the same class name as their value's class name.	2017-09-13 11:25:42 -07:00
Henry Cook	01ca3efc2b	Combine Coreplex and System Module Hierarchies (#875 ) * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless := and := * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC	2017-07-23 08:31:04 -07:00

Author

SHA1

Message

Date

Megan Wachs

f86489b59e

JTAG: Use sorted map for stability (#1073 )

* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup

2017-10-31 15:33:41 -07:00

Henry Cook

b86f4b9bb7

config: use Field defaults over Config defaults

Also rename some keys that had the same class name as their value's class name.

2017-09-13 11:25:42 -07:00

Henry Cook

01ca3efc2b

Combine Coreplex and System Module Hierarchies (#875 )

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

2017-07-23 08:31:04 -07:00

3 Commits