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Commit Graph

5 Commits

Author SHA1 Message Date
Henry Cook
7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup
Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Henry Cook
9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Yunsup Lee
6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) 2017-07-25 16:35:31 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00