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Commit Graph

8 Commits

Author SHA1 Message Date
mwachs5 a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305)
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
Andrew Waterman a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Howard Mao 49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Megan Wachs 77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Megan Wachs fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Andrew Waterman e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00