riscv/rocket-chip
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give DualCoreConfig L2 cache to speed up test runs

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This commit is contained in:
Howard Mao 2016-06-20 17:58:26 -07:00
parent daa0f3038f
commit ff43238e6e
1 changed files with 2 additions and 1 deletions
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src/main/scala/Configs.scala
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@ -529,4 +529,5 @@ class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseCo
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError }) class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config) class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
class DualCoreConfig extends Config(new WithNCores(2) ++ new BaseConfig) class DualCoreConfig extends Config(
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)