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axi4: Fragmenter cuts all input channel readys

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AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
This commit is contained in:
Wesley W. Terpstra 2017-05-01 22:52:33 -07:00
parent 3d06f01a2c
commit fe280187a1
1 changed files with 8 additions and 4 deletions
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12
src/main/scala/uncore/axi4/Fragmenter.scala
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@ -139,6 +139,10 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1) val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1) val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
// AXI ready may not depend on valid of other channels
// We cut wready here along with awready and arready before AXI4ToTL
val in_w = Queue.irrevocable(in.w, 1, flow=true)
// AR flow control; super easy // AR flow control; super easy
out.ar <> in_ar out.ar <> in_ar
out.ar.bits.user.get := Cat(in_ar.bits.user.toList ++ Seq(ar_last)) out.ar.bits.user.get := Cat(in_ar.bits.user.toList ++ Seq(ar_last))
@ -167,12 +171,12 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
// W flow control // W flow control
wbeats_ready := w_idle wbeats_ready := w_idle
out.w.valid := in.w.valid && (!wbeats_ready || wbeats_valid) out.w.valid := in_w.valid && (!wbeats_ready || wbeats_valid)
in.w.ready := out.w.ready && (!wbeats_ready || wbeats_valid) in_w.ready := out.w.ready && (!wbeats_ready || wbeats_valid)
out.w.bits := in.w.bits out.w.bits := in_w.bits
out.w.bits.last := w_last out.w.bits.last := w_last
// We should also recreate the last last // We should also recreate the last last
assert (!out.w.valid || !in.w.bits.last || w_last) assert (!out.w.valid || !in_w.bits.last || w_last)
// R flow control // R flow control
val r_last = out.r.bits.user.get(0) val r_last = out.r.bits.user.get(0)