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Merge branch 'master' into auto-plusargs

This commit is contained in:
Henry Cook
2018-02-06 18:38:44 -08:00
committed by GitHub
30 changed files with 236 additions and 166 deletions

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@ -29,25 +29,25 @@ case class ParsedInputNames(
* canonical ways of building various JVM elaboration-time structures.
*/
trait HasGeneratorUtilities {
def getConfig(names: ParsedInputNames): Config = {
new Config(names.fullConfigClasses.foldRight(Parameters.empty) { case (currentName, config) =>
def getConfig(fullConfigClassNames: Seq[String]): Config = {
new Config(fullConfigClassNames.foldRight(Parameters.empty) { case (currentName, config) =>
val currentConfig = try {
Class.forName(currentName).newInstance.asInstanceOf[Config]
} catch {
case e: java.lang.ClassNotFoundException =>
throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
throwException(s"""Unable to find part "$currentName" from "$fullConfigClassNames", did you misspell it?""", e)
}
currentConfig ++ config
})
}
def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))
def getParameters(names: Seq[String]): Parameters = getParameters(getConfig(names))
def getParameters(config: Config): Parameters = Parameters.root(config.toInstance)
def getParameters(config: Config): Parameters = config.toInstance
def elaborate(names: ParsedInputNames, params: Parameters): Circuit = {
def elaborate(fullTopModuleClassName: String, params: Parameters): Circuit = {
val gen = () =>
Class.forName(names.fullTopModuleClass)
Class.forName(fullTopModuleClassName)
.getConstructor(classOf[Parameters])
.newInstance(params)
.asInstanceOf[RawModule]
@ -69,17 +69,8 @@ trait HasGeneratorUtilities {
}
res.toString
}
def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
val f = new File(targetDir, fname)
val fw = new FileWriter(f)
fw.write(contents)
fw.close
f
}
}
/** Standardized command line interface for Scala entry point */
trait GeneratorApp extends App with HasGeneratorUtilities {
lazy val names: ParsedInputNames = {
@ -95,11 +86,10 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
}
// Canonical ways of building various JVM elaboration-time structures
lazy val td = names.targetDir
lazy val config = getConfig(names)
lazy val world = config.toInstance
lazy val params = Parameters.root(world)
lazy val circuit = elaborate(names, params)
lazy val td: String = names.targetDir
lazy val config: Config = getConfig(names.fullConfigClasses)
lazy val params: Parameters = config.toInstance
lazy val circuit: Circuit = elaborate(names.fullTopModuleClass, params)
val longName: String // Exhaustive name used to interface with external build tool targets
@ -137,6 +127,14 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
writeOutputFile(td, s"$longName.$extension", contents ())
}
}
def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
val f = new File(targetDir, fname)
val fw = new FileWriter(f)
fw.write(contents)
fw.close
f
}
}
object ElaborationArtefacts {

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@ -5,10 +5,6 @@ package freechips.rocketchip.util.property
import Chisel._
import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
import chisel3.util.{ReadyValidIO}
import freechips.rocketchip.config.{Field, Parameters}
case object PropertyLibrary extends Field[BasePropertyLibrary](new DefaultPropertyLibrary)
sealed abstract class PropertyType(name: String) {
override def toString: String = name
@ -20,7 +16,7 @@ object PropertyType {
object Cover extends PropertyType("Cover")
}
trait BasePropertyParameters {
trait BasePropertyParameters {
val pType: PropertyType
val cond: Bool
val label: String
@ -133,24 +129,30 @@ class CrossProperty(cond: Seq[Seq[CoverBoolean]], exclude: Seq[Seq[String]], mes
}
// The implementation using a setable global is bad, but removes dependence on Parameters
// This change was made in anticipation of a proper cover library
object cover {
def apply(cond: Bool)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = {
p(PropertyLibrary).generateProperty(CoverPropertyParameters(cond))
private var propLib: BasePropertyLibrary = new DefaultPropertyLibrary
def setPropLib(lib: BasePropertyLibrary): Unit = this.synchronized {
propLib = lib
}
def apply(cond: Bool, label: String)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = {
p(PropertyLibrary).generateProperty(CoverPropertyParameters(cond, label))
def apply(cond: Bool)(implicit sourceInfo: SourceInfo): Unit = {
propLib.generateProperty(CoverPropertyParameters(cond))
}
def apply(cond: Bool, label: String, message: String)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = {
p(PropertyLibrary).generateProperty(CoverPropertyParameters(cond, label, message))
def apply(cond: Bool, label: String)(implicit sourceInfo: SourceInfo): Unit = {
propLib.generateProperty(CoverPropertyParameters(cond, label))
}
def apply(prop: BaseProperty)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = {
def apply(cond: Bool, label: String, message: String)(implicit sourceInfo: SourceInfo): Unit = {
propLib.generateProperty(CoverPropertyParameters(cond, label, message))
}
def apply(prop: BaseProperty)(implicit sourceInfo: SourceInfo): Unit = {
prop.generateProperties().foreach( (pp: BasePropertyParameters) => {
if (pp.pType == PropertyType.Cover) {
p(PropertyLibrary).generateProperty(CoverPropertyParameters(pp.cond, pp.label, pp.message))
propLib.generateProperty(CoverPropertyParameters(pp.cond, pp.label, pp.message))
}
})
}
def apply[T <: Data](rv: ReadyValidIO[T], label: String, message: String)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = {
def apply[T <: Data](rv: ReadyValidIO[T], label: String, message: String)(implicit sourceInfo: SourceInfo): Unit = {
apply( rv.valid && rv.ready, label + "_FIRE", message + ": valid and ready")
apply( rv.valid && !rv.ready, label + "_STALL", message + ": valid and not ready")
apply(!rv.valid && rv.ready, label + "_IDLE", message + ": not valid and ready")

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@ -3,6 +3,7 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{withClockAndReset}
/** Reset: asynchronous assert,
* synchronous de-assert
@ -28,12 +29,12 @@ object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.clock := clk
catcher.reset := rst
catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
catcher.io.sync_reset
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))