riscv/rocket-chip
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Merge branch 'master' into auto-plusargs

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This commit is contained in:
Henry Cook
2018-02-06 18:38:44 -08:00
committed by GitHub
parent 355d3b15e8 9f6d586e8c
commit fe277cf6f0
30 changed files with 236 additions and 166 deletions
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2
src/main/scala/tilelink/Bundles.scala
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@ -76,7 +76,7 @@ object TLPermissions
def BtoN = UInt(2, cWidth)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck)
// Report types (ProbeAck, Release)
def TtoT = UInt(3, cWidth)
def BtoB = UInt(4, cWidth)
def NtoN = UInt(5, cWidth)

4
src/main/scala/tilelink/SourceShrinker.scala
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@ -18,8 +18,8 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
sourceId = IdRange(0, maxInFlight))
val node = TLAdapterNode(
// We erase all client information since we crush the source Ids
clientFn = { _ => TLClientPortParameters(clients = Seq(client)) },
managerFn = { mp => mp.copy(managers = mp.managers.map(_.copy(fifoId = None))) })
clientFn = { cp => TLClientPortParameters(clients = Seq(client.copy(requestFifo = cp.clients.exists(_.requestFifo)))) },
managerFn = { mp => mp.copy(managers = mp.managers.map(m => m.copy(fifoId = if (maxInFlight==1) Some(0) else m.fifoId))) })
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>