riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge branch 'master' into auto-plusargs

Browse Source
This commit is contained in:
Henry Cook
2018-02-06 18:38:44 -08:00
committed by GitHub
parent 355d3b15e8 9f6d586e8c
commit fe277cf6f0
30 changed files with 236 additions and 166 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocket/RocketCore.scala
View File

@ -545,7 +545,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
val tval_valid = wb_xcpt && wb_cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
io.ptw.ptbr := csr.io.ptbr
io.ptw.status := csr.io.status
io.ptw.pmp := csr.io.pmp