riscv/rocket-chip
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Add a way to create Async Reset Registers and a way to easily access them with TL2

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Megan Wachs committed 2016-09-08 20:02:07 -07:00
1 parent c1eb1f12a2
commit fda4c2bd76
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vsim/Makefrag
+2 -1
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@@ -6,7 +6,8 @@
bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/AsyncMailbox.v
$(base_dir)/vsrc/AsyncMailbox.v \
$(base_dir)/vsrc/AsyncResetReg.v
sim_vsrcs = \
$(generated_dir)/$(MODEL).$(CONFIG).v \