riscv/rocket-chip
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icache: back-pressure is unnecessary (#564)

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* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
This commit is contained in:
Wesley W. Terpstra 2017-02-24 21:01:56 -08:00 committed by GitHub
parent 87d909e996
commit fd972f5c67
1 changed files with 2 additions and 1 deletions
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src/main/scala/rocket/ICache.scala
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@ -95,7 +95,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
val refill_tag = refill_addr(tagBits+untagBits-1,untagBits) val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d) val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d)
tl_out.d.ready := state === s_refill tl_out.d.ready := Bool(true)
require (edge.manager.minLatency > 0)
val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0) val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
val entagbits = code.width(tagBits) val entagbits = code.width(tagBits)