riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

overlapping read/resps in l2 fix

Browse Source
This commit is contained in:
Henry Cook 2015-03-17 02:10:30 -07:00
parent 2d33dd8e6e
commit fd8f6ff026
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
uncore/src/main/scala/cache.scala
View File

@ -900,6 +900,11 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
mergeDataInternal(io.data.resp.bits.addr_beat, io.data.resp.bits.data)
pending_resps := pending_resps & ~UIntToOH(io.data.resp.bits.addr_beat)
}
when(io.data.read.ready && io.data.resp.valid) {
pending_resps := (pending_resps &
~UIntToOH(io.data.resp.bits.addr_beat)) |
UIntToOH(curr_read_beat)
}
}
is(s_data_resp) {
when(io.data.resp.valid) {