Merge branch 'master' of github.com:ucb-bar/reference-chip
This commit is contained in:
Ben Keller
commit
fcfc1078f8
33
Makefrag
33
Makefrag
@ -1,8 +1,10 @@
|
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# Makefile snippet used by emulator/vlsi/fpga backends
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asm_timeout_cycles = 10000000
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bmark_timeout_cycles = 100000000
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MODEL := Top
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CXX := g++
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CXXFLAGS := -O2
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CXXFLAGS := -O1
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||||
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
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@ -215,6 +217,9 @@ vecasm_p_tests = \
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rv64uv-p-vmsv \
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rv64uv-p-vmvv \
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rv64uv-p-vfmvv \
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rv64uv-p-vsetcfg \
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||||
rv64uv-p-vsetcfgi \
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rv64uv-p-vsetvl \
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rv64uv-p-movz \
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rv64uv-p-movn \
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rv64uv-p-fmovz \
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@ -241,21 +246,23 @@ vecasm_p_tests = \
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rv64uv-p-vvadd_w \
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rv64uv-p-vvmul_d \
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rv64uv-p-amoadd_d \
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rv64uv-p-amoswap_d \
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rv64uv-p-amoand_d \
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rv64uv-p-amoor_d \
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rv64uv-p-amoxor_d \
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rv64uv-p-amomax_d \
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rv64uv-p-amomin_d \
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rv64uv-p-amomaxu_d \
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rv64uv-p-amominu_d \
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rv64uv-p-amoswap_d \
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rv64uv-p-amoadd_w \
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rv64uv-p-amoswap_w \
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rv64uv-p-amoand_w \
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rv64uv-p-amoor_w \
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rv64uv-p-amoxor_w \
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rv64uv-p-amomax_w \
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rv64uv-p-amomin_w \
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rv64uv-p-amomaxu_w \
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rv64uv-p-amominu_w \
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rv64uv-p-amoswap_w \
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rv64uv-p-imul \
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rv64uv-p-fma \
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rv64ui-p-vec-mul \
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@ -299,15 +306,15 @@ vecasm_p_tests = \
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rv64uf-p-vec-fcvt_w \
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rv64uf-p-vec-fcvt \
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rv64uf-p-vec-fcmp \
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rv64sv-p-illegal_tvec_cmd \
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rv64sv-p-illegal_tvec_regid \
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rv64sv-p-illegal_vt_inst \
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rv64sv-p-illegal_vt_regid \
|
||||
rv64sv-p-ma_utld \
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rv64sv-p-ma_utsd \
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rv64sv-p-ma_vld \
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rv64sv-p-ma_vsd \
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rv64sv-p-ma_vt_inst \
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# rv64sv-p-illegal_tvec_cmd \
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# rv64sv-p-illegal_tvec_regid \
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# rv64sv-p-illegal_vt_inst \
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# rv64sv-p-illegal_vt_regid \
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# rv64sv-p-ma_utld \
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# rv64sv-p-ma_utsd \
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# rv64sv-p-ma_vld \
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# rv64sv-p-ma_vsd \
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# rv64sv-p-ma_vt_inst \
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vecasm_v_tests = \
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rv64uv-v-wakeup \
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@ -591,5 +598,5 @@ bt_vvadd.riscv\
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disasm := 2>
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which_disasm := $(shell which riscv-dis)
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ifneq ($(which_disasm),)
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disasm := 3>&1 1>&2 2>&3 | $(which_disasm) >
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disasm := 3>&1 1>&2 2>&3 | $(which_disasm) --extension=hwacha >
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endif
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|
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5
README
5
README
@ -2,10 +2,7 @@ Quick and dirty instructions:
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|
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CHECKOUT THE CODE:
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git submodule update --init
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cd riscv-tools
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git submodule update --init
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git submodule update --init --recursive
|
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|
||||
|
||||
BUILDING THE TOOLCHAIN:
|
||||
|
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2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 3b1979d8a182d9fa8a65ce0523581f353f9f4603
|
||||
Subproject commit 56e8b23ff2d3336177f9e7d941f3d22200301ad0
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@ -18,22 +18,30 @@ DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
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CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
|
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CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
|
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|
||||
generated-src/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
|
||||
|
||||
generated-src-debug/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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||||
generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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||||
cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
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||||
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||||
$(MODEL).o: %.o: generated-src/%.cpp
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$(MODEL).o: %.o: generated-src/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) -o $@
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|
||||
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp)) -o $@
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||||
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$(wildcard generated-src/*.o): %.o: %.cpp generated-src/$(MODEL).h
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$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
|
||||
|
||||
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp
|
||||
$(wildcard generated-src-debug/*.o): %.o: %.cpp generated-src-debug/$(MODEL).h
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$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
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||||
|
||||
$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).cpp
|
||||
$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).h
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||||
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
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||||
|
||||
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).cpp
|
||||
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).h
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$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
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||||
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emulator: $(OBJS) libdramsim.a
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||||
@ -74,15 +82,15 @@ output:
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||||
mkdir -p $@
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||||
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output/%.run: output/%.hex emulator
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||||
./emulator +dramsim +max-cycles=30000000 +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
|
||||
./emulator +dramsim +max-cycles=$(bmark_timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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||||
|
||||
output/%.out: output/%.hex emulator
|
||||
./emulator +dramsim +max-cycles=30000000 +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
|
||||
./emulator +dramsim +max-cycles=$(bmark_timeout_cycles) +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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||||
|
||||
output/%.vpd: output/%.hex emulator-debug
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rm -rf $@.vcd && mkfifo $@.vcd
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||||
vcd2vpd $@.vcd $@ > /dev/null &
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||||
./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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||||
./emulator-debug +dramsim +max-cycles=$(bmark_timeout_cycles) +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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|
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run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
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@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
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||||
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||||
@ -1 +1 @@
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||||
Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c
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||||
Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118
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@ -30,7 +30,8 @@ object BuildSettings extends Build {
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lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
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lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
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lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
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lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
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lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket)
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lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
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val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
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val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
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@ -46,7 +47,7 @@ object BuildSettings extends Build {
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val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
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val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
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val chiselArgs = args.drop(numArgs)
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val component = classLoader.loadClass(packageName+"."+componentName)
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val component = classLoader.loadClass((if (!componentName.contains('.')) packageName+"." else "")+componentName)
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val generator = () => component.newInstance()
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chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
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}
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||||
@ -1 +1 @@
|
||||
Subproject commit df4967acd1a511517977feb63eabd647e6a00701
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||||
Subproject commit 32f14433d48215501d2fccf02614d1879abfbdb1
|
||||
@ -1 +1 @@
|
||||
Subproject commit 78f57c3fd83bea98b716b07898d2c21ebc36f064
|
||||
Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d
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||||
2
rocket
2
rocket
@ -1 +1 @@
|
||||
Subproject commit cceb29c281b6fc8d5aa1ac025d18854db13f10bb
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||||
Subproject commit f08e60a16598deb32ddfb9eb9450463842555bab
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||||
@ -83,7 +83,7 @@ class ReferenceChipBackend extends VerilogBackend
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transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
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}
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||||
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||||
class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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||||
class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
|
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{
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||||
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
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||||
val io = new Bundle {
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||||
@ -101,10 +101,10 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
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||||
//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
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||||
val mem_serdes = Module(new MemSerdes(htif_width))
|
||||
|
||||
require(clientEndpoints.length == ln.nClients)
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||||
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
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net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
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val net = Module(new ReferenceChipCrossbarNetwork)
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||||
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
|
||||
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
|
||||
|
||||
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
|
||||
@ -145,7 +145,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
|
||||
|
||||
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
|
||||
|
||||
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
|
||||
class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
|
||||
{
|
||||
implicit val tl = conf.tl
|
||||
val io = new Bundle {
|
||||
@ -158,7 +158,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
|
||||
val mem_backup_en = Bool(INPUT)
|
||||
}
|
||||
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
|
||||
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
|
||||
val outmemsys = Module(new OuterMemorySystem(htif_width))
|
||||
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
|
||||
outmemsys.io.incoherent := incoherentWithHtif
|
||||
htif.io.cpu <> io.htif
|
||||
@ -246,7 +246,7 @@ class Top extends Module {
|
||||
else new MICoherence
|
||||
}
|
||||
|
||||
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
|
||||
implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
|
||||
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
|
||||
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
|
||||
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
|
||||
@ -254,14 +254,18 @@ class Top extends Module {
|
||||
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
|
||||
val dc = DCacheConfig(128, 4, ntlb = 8,
|
||||
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
|
||||
val vic = ICacheConfig(128, 1)
|
||||
val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
|
||||
val rc = RocketConfiguration(tl, ic, dc,
|
||||
fpu = HAS_FPU)
|
||||
fpu = HAS_FPU
|
||||
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
|
||||
)
|
||||
|
||||
val io = new VLSITopIO(HTIF_WIDTH)
|
||||
|
||||
val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
||||
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
||||
val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
|
||||
val uncore = Module(new Uncore(HTIF_WIDTH))
|
||||
|
||||
for (i <- 0 until uc.nTiles) {
|
||||
val hl = uncore.io.htif(i)
|
||||
|
||||
@ -5,7 +5,7 @@ import Node._
|
||||
import uncore._
|
||||
import rocket._
|
||||
|
||||
class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
|
||||
class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
|
||||
{
|
||||
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
|
||||
val io = new Bundle {
|
||||
@ -15,11 +15,11 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
|
||||
val mem = new ioMem
|
||||
}
|
||||
|
||||
require(clientEndpoints.length == ln.nClients)
|
||||
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
|
||||
|
||||
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
|
||||
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
val net = Module(new ReferenceChipCrossbarNetwork)
|
||||
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
|
||||
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
|
||||
|
||||
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
|
||||
@ -35,7 +35,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
|
||||
conv.io.mem.resp <> Queue(io.mem.resp)
|
||||
}
|
||||
|
||||
class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
|
||||
class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
|
||||
{
|
||||
implicit val (tl, ln) = (conf.tl, conf.tl.ln)
|
||||
val io = new Bundle {
|
||||
@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
|
||||
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
|
||||
}
|
||||
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
|
||||
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
|
||||
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
|
||||
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
|
||||
outmemsys.io.incoherent := incoherentWithHtif
|
||||
htif.io.cpu <> io.htif
|
||||
@ -85,7 +85,7 @@ class FPGATop extends Module {
|
||||
val ntiles = 1
|
||||
val nbanks = 1
|
||||
val nmshrs = 2
|
||||
implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1)
|
||||
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1)
|
||||
implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS)
|
||||
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
|
||||
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64)
|
||||
@ -100,7 +100,7 @@ class FPGATop extends Module {
|
||||
|
||||
val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
||||
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
||||
val uncore = Module(new FPGAUncore(htif_width, tileList))
|
||||
val uncore = Module(new FPGAUncore(htif_width))
|
||||
|
||||
for (i <- 0 until uc.nTiles) {
|
||||
val hl = uncore.io.htif(i)
|
||||
|
||||
@ -3,25 +3,26 @@ package referencechip
|
||||
import Chisel._
|
||||
import uncore._
|
||||
import scala.reflect._
|
||||
import scala.reflect.runtime.universe._
|
||||
|
||||
object TileLinkHeaderAppender {
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
def apply[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](in: PairedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert))
|
||||
shim.io.in <> in
|
||||
shim.io.out
|
||||
}
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert))
|
||||
shim.io.in.meta <> in
|
||||
shim.io.out.meta
|
||||
}
|
||||
}
|
||||
|
||||
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
|
||||
class TileLinkHeaderAppender[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
|
||||
implicit val ln = conf.ln
|
||||
val io = new Bundle {
|
||||
val in = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
|
||||
val out = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
|
||||
val in = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
|
||||
val out = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
|
||||
}
|
||||
|
||||
val meta_q = Queue(io.in.meta)
|
||||
@ -93,11 +94,21 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfi
|
||||
io.mem.req_data <> mem_data_q.io.deq
|
||||
}
|
||||
|
||||
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) {
|
||||
class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) {
|
||||
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
|
||||
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}}))
|
||||
val io = new Bundle {
|
||||
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
|
||||
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
|
||||
}
|
||||
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
|
||||
|
||||
// Actually instantiate the particular networks required for TileLink
|
||||
val acqNet = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, (acq: PhysicalNetworkIO[Acquire]) => co.messageHasData(acq.payload)))
|
||||
val relNet = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, (rel: PhysicalNetworkIO[Release]) => co.messageHasData(rel.payload)))
|
||||
val probeNet = Module(new BasicCrossbar(new Probe))
|
||||
val grantNet = Module(new BasicCrossbar(new Grant))
|
||||
val ackNet = Module(new BasicCrossbar(new GrantAck))
|
||||
|
||||
// Aliases for the various network IO bundle types
|
||||
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
|
||||
type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
|
||||
@ -163,61 +174,53 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
|
||||
phys_in.valid := Bool(false)
|
||||
}
|
||||
|
||||
// Use reflection to determine whether a particular endpoint should be
|
||||
// hooked up as an [input/output] for a FIFO nework that is transmiitting
|
||||
// [client/master]-sourced messages.
|
||||
def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
|
||||
// Is end's type a subtype of S, the agent type associated with inputs?
|
||||
if(classTag[S].runtimeClass.isInstance(end))
|
||||
doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
|
||||
else
|
||||
doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
|
||||
def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
|
||||
if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim)
|
||||
else doFIFOOutputHookup(physIn, physOut, logIO, outShim)
|
||||
}
|
||||
|
||||
def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
|
||||
doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
|
||||
|
||||
def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
|
||||
doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
|
||||
|
||||
// Use reflection to determine whether a particular endpoint should be
|
||||
// hooked up as an [input/output] for a Paired nework that is transmiitting
|
||||
// [client/master]-sourced messages.
|
||||
def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
|
||||
// Is end's type a subtype of S, the agent type associated with inputs?
|
||||
if(classTag[S].runtimeClass.isInstance(end)) {
|
||||
doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
|
||||
doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
|
||||
} else {
|
||||
doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
|
||||
doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
|
||||
//Hookup all instances of a particular subbundle of
|
||||
def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = {
|
||||
typeTag[T].tpe match{
|
||||
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
}
|
||||
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
}
|
||||
case _ => require(false, "Unknown message sourcing.")
|
||||
}
|
||||
}
|
||||
|
||||
def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
|
||||
doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
|
||||
def doPairedDataHookup[T <: Data, R <: Data](isEndpointSourceOfMessage: Boolean, physIn: PBCIO[T,R], physOut: PBCIO[T,R], logIO: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
|
||||
if(isEndpointSourceOfMessage) {
|
||||
doFIFOInputHookup[T](physIn.meta, physOut.meta, logIO.meta, inShim)
|
||||
doFIFOInputHookup[R](physIn.data, physOut.data, logIO.data, inShimD)
|
||||
} else {
|
||||
doFIFOOutputHookup[T](physIn.meta, physOut.meta, logIO.meta, outShim)
|
||||
doFIFOOutputHookup[R](physIn.data, physOut.data, logIO.data, outShimD)
|
||||
}
|
||||
}
|
||||
|
||||
def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
|
||||
doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
|
||||
def doPairedDataHookups[T <: Data: TypeTag, R <: Data](physIO: PairedCrossbarIO[T,R], getLogIO: TileLinkIO => PLNIO[T,R]) = {
|
||||
typeTag[T].tpe match{
|
||||
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
}
|
||||
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
}
|
||||
case _ => require(false, "Unknown message sourcing.")
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Actually instantiate the particular networks required for TileLink
|
||||
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
|
||||
val acq_net = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, acqHasData _))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
|
||||
|
||||
def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
|
||||
val rel_net = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, relHasData _))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
|
||||
|
||||
val probe_net = Module(new BasicCrossbar(new Probe))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
|
||||
|
||||
val grant_net = Module(new BasicCrossbar(new Grant))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
|
||||
|
||||
val ack_net = Module(new BasicCrossbar(new GrantAck))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
|
||||
|
||||
val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
|
||||
doPairedDataHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
|
||||
doPairedDataHookups(relNet.io, (tl: TileLinkIO) => tl.release)
|
||||
doFIFOHookups(probeNet.io, (tl: TileLinkIO) => tl.probe)
|
||||
doFIFOHookups(grantNet.io, (tl: TileLinkIO) => tl.grant)
|
||||
doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
|
||||
}
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a
|
||||
Subproject commit 803308e917397776444c3e3696fbfacad709a1db
|
||||
Loading…
Reference in New Issue
Block a user