riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

graphML: reverse interrupt arrows

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-04-14 16:17:56 -07:00
parent d3925f0998
commit fcf774f125
3 changed files with 17 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/diplomacy/LazyModule.scala
View File

@ -97,9 +97,19 @@ abstract class LazyModule()(implicit val p: Parameters)
nodes.filter(!_.omitGraphML) foreach { n => n.outputs.filter(!_._1.omitGraphML).foreach { case (o, l) =>
buf ++= pad
buf ++= "<edge"
if (o.reverse) {
buf ++= s""" target=\"${index}::${n.index}\""""
buf ++= s""" source=\"${o.lazyModule.index}::${o.index}\">"""
} else {
buf ++= s""" source=\"${index}::${n.index}\""""
buf ++= s""" target=\"${o.lazyModule.index}::${o.index}\"><data key=\"e\"><y:PolyLineEdge>"""
buf ++= s""" target=\"${o.lazyModule.index}::${o.index}\">"""
}
buf ++= s"""<data key=\"e\"><y:PolyLineEdge>"""
if (o.reverse) {
buf ++= s"""<y:Arrows source=\"standard\" target=\"none\"/>"""
} else {
buf ++= s"""<y:Arrows source=\"none\" target=\"standard\"/>"""
}
buf ++= s"""<y:LineStyle color=\"${o.colour}\" type=\"line\" width=\"1.0\"/>"""
buf ++= s"""<y:EdgeLabel modelName=\"centered\" rotationAngle=\"270.0\">${l}</y:EdgeLabel>"""
buf ++= s"""</y:PolyLineEdge></data></edge>\n"""

3
src/main/scala/diplomacy/Nodes.scala
View File

@ -17,6 +17,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
def edgeI(pd: DI, pu: UI): EI
def bundleI(ei: EI): BI
def colour: String
def reverse: Boolean = false
def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => bindings().foreach { case (_, i, o) => i <> o })
}
@ -67,6 +68,7 @@ abstract class BaseNode
protected[diplomacy] def outputs: Seq[(BaseNode, String)]
protected[diplomacy] def inputs: Seq[(BaseNode, String)]
protected[diplomacy] def colour: String
protected[diplomacy] def reverse: Boolean
}
case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
@ -261,6 +263,7 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
// meta-data for printing the node graph
protected[diplomacy] def colour = inner.colour
protected[diplomacy] def reverse = inner.reverse
protected[diplomacy] def outputs = oPorts.map(_._2) zip edgesOut.map(e => outer.labelO(e))
protected[diplomacy] def inputs = iPorts.map(_._2) zip edgesIn .map(e => inner.labelI(e))
}

1
src/main/scala/uncore/tilelink2/IntNodes.scala
View File

@ -70,6 +70,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool())
def colour = "#0000ff" // blue
override def reverse = true
override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString
override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString