From 22345dd07309e73ce66f72097c6a661bd06afd6d Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 22 Feb 2014 22:53:24 -0800 Subject: [PATCH 01/42] push rocket,hwacha --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 41023dc1..a508bfc8 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 41023dc10f37aca4d501c9f9b9edb5992d8e2bd9 +Subproject commit a508bfc8c9a32f18d798117b9705fdc43392ffa7 From 8acc9510c49143e9b21d74173a7bba97904b6b2d Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 24 Feb 2014 01:43:55 -0800 Subject: [PATCH 02/42] push hwacha,chisel --- chisel | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel b/chisel index 9650d7e6..56e8b23f 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 9650d7e69ed2979a8c12732c8254c3bb12cf2557 +Subproject commit 56e8b23ff2d3336177f9e7d941f3d22200301ad0 From e5c2bd5e7b34cd8c3771fb239adc427e39dbbcbf Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 25 Feb 2014 03:50:32 -0800 Subject: [PATCH 03/42] add extensions option to riscv-dis for better disassembly --- Makefrag | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefrag b/Makefrag index aee19ed4..1eb34d55 100644 --- a/Makefrag +++ b/Makefrag @@ -598,5 +598,5 @@ bt_vvadd.riscv\ disasm := 2> which_disasm := $(shell which riscv-dis) ifneq ($(which_disasm),) - disasm := 3>&1 1>&2 2>&3 | $(which_disasm) > + disasm := 3>&1 1>&2 2>&3 | $(which_disasm) --extension=hwacha > endif diff --git a/riscv-tools b/riscv-tools index 16908b2a..cc599fce 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 16908b2a8dcf9e8b4e3fdf1c962e123067356dba +Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d From 220076506c4a798c03b4a718074b513796ec037b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 25 Feb 2014 03:51:15 -0800 Subject: [PATCH 04/42] push hwacha; all vector p/v/pt tests work now --- riscv-tests | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index c50db79a..32f14433 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit c50db79a8e549d7dd2112ff22d48be5e4b501fea +Subproject commit 32f14433d48215501d2fccf02614d1879abfbdb1 diff --git a/rocket b/rocket index a508bfc8..f08e60a1 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit a508bfc8c9a32f18d798117b9705fdc43392ffa7 +Subproject commit f08e60a16598deb32ddfb9eb9450463842555bab From a5625de3d59b3cb1c8ccbf316675bf4d28e92b3b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 25 Feb 2014 21:18:03 -0800 Subject: [PATCH 05/42] support vector irq tests --- Makefrag | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/Makefrag b/Makefrag index 1eb34d55..49109614 100644 --- a/Makefrag +++ b/Makefrag @@ -306,15 +306,18 @@ vecasm_p_tests = \ rv64uf-p-vec-fcvt_w \ rv64uf-p-vec-fcvt \ rv64uf-p-vec-fcmp \ -# rv64sv-p-illegal_tvec_cmd \ -# rv64sv-p-illegal_tvec_regid \ -# rv64sv-p-illegal_vt_inst \ -# rv64sv-p-illegal_vt_regid \ -# rv64sv-p-ma_utld \ -# rv64sv-p-ma_utsd \ -# rv64sv-p-ma_vld \ -# rv64sv-p-ma_vsd \ -# rv64sv-p-ma_vt_inst \ + rv64sv-p-illegal_cfg_nxpr \ + rv64sv-p-illegal_cfg_nfpr \ + rv64sv-p-illegal_inst \ + rv64sv-p-illegal_tvec_regid \ + rv64sv-p-illegal_vt_inst \ + rv64sv-p-illegal_vt_regid \ + rv64sv-p-ma_utld \ + rv64sv-p-ma_utsd \ + rv64sv-p-ma_vld \ + rv64sv-p-ma_vsd \ + rv64sv-p-ma_vt_inst \ + rv64sv-p-privileged_inst \ vecasm_v_tests = \ rv64uv-v-wakeup \ From 46714c0c606594df0daadc360e5ff44f74168727 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 26 Feb 2014 21:20:53 -0800 Subject: [PATCH 06/42] more improvements to hwacha --- Makefrag | 3 +++ riscv-tests | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefrag b/Makefrag index 49109614..4d68b1ac 100644 --- a/Makefrag +++ b/Makefrag @@ -265,6 +265,7 @@ vecasm_p_tests = \ rv64uv-p-amoswap_w \ rv64uv-p-imul \ rv64uv-p-fma \ + rv64uv-p-fma_many \ rv64ui-p-vec-mul \ rv64ui-p-vec-mulw \ rv64ui-p-vec-mulh \ @@ -369,6 +370,7 @@ vecasm_v_tests = \ rv64uv-v-amominu_w \ rv64uv-v-imul \ rv64uv-v-fma \ + rv64uv-v-fma_many \ rv64ui-v-vec-mul \ rv64ui-v-vec-mulw \ rv64ui-v-vec-mulh \ @@ -461,6 +463,7 @@ vecasm_pt_tests = \ rv64uv-pt-amominu_w \ rv64uv-pt-imul \ rv64uv-pt-fma \ + rv64uv-pt-fma_many \ rv64ui-pt-vec-mul \ rv64ui-pt-vec-mulw \ rv64ui-pt-vec-mulh \ diff --git a/riscv-tests b/riscv-tests index 32f14433..3e400b04 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 32f14433d48215501d2fccf02614d1879abfbdb1 +Subproject commit 3e400b04627aacf42cfc6bc05efce22f67bdd788 From bcfcdefe88e9a15ab5c3e405acf3115a477f65c8 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 27 Feb 2014 04:39:12 -0800 Subject: [PATCH 07/42] update hwacha --- Makefrag | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefrag b/Makefrag index 4d68b1ac..68d14b73 100644 --- a/Makefrag +++ b/Makefrag @@ -220,6 +220,7 @@ vecasm_p_tests = \ rv64uv-p-vsetcfg \ rv64uv-p-vsetcfgi \ rv64uv-p-vsetvl \ + rv64uv-p-keepcfg \ rv64uv-p-movz \ rv64uv-p-movn \ rv64uv-p-fmovz \ From 0c4442c172eccf84ac4db5df90f420027dbeb809 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 27 Feb 2014 20:28:19 -0800 Subject: [PATCH 08/42] push tests/tools --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index 3e400b04..68174507 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 3e400b04627aacf42cfc6bc05efce22f67bdd788 +Subproject commit 681745071f7427b9b65919214547e20a12834360 diff --git a/riscv-tools b/riscv-tools index cc599fce..116e2f99 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d +Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9 From 8c459df3b601f3c6b81d5f5f199d640a68d1e4b1 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 28 Feb 2014 22:50:34 -0800 Subject: [PATCH 09/42] flush deck when xcpt occurs, fixes remaining p test bugs --- riscv-tools | 2 +- src/main/scala/RocketChip.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tools b/riscv-tools index 116e2f99..cc599fce 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9 +Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 4cf98468..d258113b 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -258,7 +258,7 @@ class Top extends Module { val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU - //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + ,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) val io = new VLSITopIO(HTIF_WIDTH) From e20d50436ab8093306dbafa51ccb91660539f423 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 1 Mar 2014 00:01:35 -0800 Subject: [PATCH 10/42] committed in the wrong directory, meant to commit in the hwacha directory --- src/main/scala/RocketChip.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d258113b..4cf98468 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -258,7 +258,7 @@ class Top extends Module { val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU - ,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) val io = new VLSITopIO(HTIF_WIDTH) From 49f0e43ed1783f40d2a821de47dc16747868df9f Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 1 Mar 2014 03:31:03 -0800 Subject: [PATCH 11/42] push riscv-tools --- riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tools b/riscv-tools index cc599fce..116e2f99 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d +Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9 From 23045ec37966d965ce7ea0c786a619eacd89f84d Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sun, 2 Mar 2014 03:38:06 -0800 Subject: [PATCH 12/42] add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv --- Makefrag | 14 ++++++++++++++ riscv-tests | 2 +- riscv-tools | 2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Makefrag b/Makefrag index 68d14b73..0ef0653c 100644 --- a/Makefrag +++ b/Makefrag @@ -217,6 +217,8 @@ vecasm_p_tests = \ rv64uv-p-vmsv \ rv64uv-p-vmvv \ rv64uv-p-vfmvv \ + rv64uv-p-vfmsv_d \ + rv64uv-p-vfmsv_s \ rv64uv-p-vsetcfg \ rv64uv-p-vsetcfgi \ rv64uv-p-vsetvl \ @@ -328,6 +330,12 @@ vecasm_v_tests = \ rv64uv-v-vmsv \ rv64uv-v-vmvv \ rv64uv-v-vfmvv \ + rv64uv-v-vfmsv_d \ + rv64uv-v-vfmsv_s \ + rv64uv-v-vsetcfg \ + rv64uv-v-vsetcfgi \ + rv64uv-v-vsetvl \ + rv64uv-v-keepcfg \ rv64uv-v-movz \ rv64uv-v-movn \ rv64uv-v-fmovz \ @@ -427,6 +435,12 @@ vecasm_pt_tests = \ rv64uv-pt-vmvv \ rv64uv-pt-vmsv \ rv64uv-pt-vfmvv \ + rv64uv-pt-vfmsv_d \ + rv64uv-pt-vfmsv_s \ + rv64uv-pt-vsetcfg \ + rv64uv-pt-vsetcfgi \ + rv64uv-pt-vsetvl \ + rv64uv-pt-keepcfg \ rv64uv-pt-movz \ rv64uv-pt-movn \ rv64uv-pt-fmovz \ diff --git a/riscv-tests b/riscv-tests index 68174507..ea6edc71 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 681745071f7427b9b65919214547e20a12834360 +Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c diff --git a/riscv-tools b/riscv-tools index 116e2f99..ebb909ab 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9 +Subproject commit ebb909ab9dfff8387449faa5827d47eda693b70b From d055c0ebaf2946d025c95c6ca809c51fcf655d5d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 4 Mar 2014 16:38:34 -0800 Subject: [PATCH 13/42] Push rocket/hardfloat/chisel --- chisel | 2 +- csrc/emulator.cc | 2 +- hardfloat | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 4 ++-- src/main/scala/fpga.scala | 5 ++--- 6 files changed, 8 insertions(+), 9 deletions(-) diff --git a/chisel b/chisel index 56e8b23f..25a33ba1 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 56e8b23ff2d3336177f9e7d941f3d22200301ad0 +Subproject commit 25a33ba1d456294fe4ebc79fe95339a0d9d20e8a diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 19d9fe92..6b90d469 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -125,7 +125,7 @@ int main(int argc, char** argv) } if (log) - tile.print(stderr, stderr); + tile.print(stderr); if (vcd) tile.dump(vcdfile, trace_count); diff --git a/hardfloat b/hardfloat index d1269259..39a08130 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118 +Subproject commit 39a08130d41ceb9e7f98fa7092fc38970009a460 diff --git a/rocket b/rocket index f08e60a1..49f633cd 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit f08e60a16598deb32ddfb9eb9450463842555bab +Subproject commit 49f633cd12de6e69479943d8089563edae7e03f5 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 4cf98468..9355a8ed 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -256,8 +256,8 @@ class Top extends Module { nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) val vic = ICacheConfig(128, 1) val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val rc = RocketConfiguration(tl, ic, dc, - fpu = HAS_FPU + val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None + val rc = RocketConfiguration(tl, ic, dc, fpu //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 108534f7..f454fe0a 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -92,9 +92,8 @@ class FPGATop extends Module { val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates) - val rc = RocketConfiguration(tl, ic, dc, - fastMulDiv = false, - fpu = false) + val rc = RocketConfiguration(tl, ic, dc, fpu = None, + fastMulDiv = false) val io = new FPGATopIO(htif_width) From 6951333a084bb1386da9402a4ad27e85d58df520 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 4 Mar 2014 23:43:00 -0800 Subject: [PATCH 14/42] push rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 49f633cd..004dc6f5 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 49f633cd12de6e69479943d8089563edae7e03f5 +Subproject commit 004dc6f502d88f83580261bfbd88d2e3ebd727c8 From f04bde75fb88d9aabac7f713856efb6df9a50a69 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 19:12:20 -0700 Subject: [PATCH 15/42] New FP encoding --- Makefrag | 2 ++ chisel | 2 +- riscv-tools | 2 +- rocket | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Makefrag b/Makefrag index 0ef0653c..497b04b2 100644 --- a/Makefrag +++ b/Makefrag @@ -109,6 +109,7 @@ asm_p_tests = \ rv64uf-p-fcmp \ rv64uf-p-fcvt \ rv64uf-p-fcvt_w \ + rv64uf-p-fclass \ rv64uf-p-fadd \ rv64uf-p-fmin \ rv64uf-p-fmadd \ @@ -205,6 +206,7 @@ asm_v_tests = \ rv64uf-v-fcmp \ rv64uf-v-fcvt \ rv64uf-v-fcvt_w \ + rv64uf-v-fclass \ rv64uf-v-fadd \ rv64uf-v-fmin \ rv64uf-v-fmadd \ diff --git a/chisel b/chisel index 25a33ba1..9ceee822 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 25a33ba1d456294fe4ebc79fe95339a0d9d20e8a +Subproject commit 9ceee82282839f0dd2d11eb13b59b0a9245944cc diff --git a/riscv-tools b/riscv-tools index ebb909ab..85dad284 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit ebb909ab9dfff8387449faa5827d47eda693b70b +Subproject commit 85dad28489c39eb0ea2bc4ef3dc86b9fd8f75ca5 diff --git a/rocket b/rocket index 004dc6f5..76b583c8 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 004dc6f502d88f83580261bfbd88d2e3ebd727c8 +Subproject commit 76b583c8f3d279c4c9f0eea0947df25dec2ef5fb From 7ac003a4f754042f03d9f16c85223a5d4fbed238 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 20:36:39 -0700 Subject: [PATCH 16/42] push hardfloat --- hardfloat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardfloat b/hardfloat index 39a08130..2a05ecbb 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 39a08130d41ceb9e7f98fa7092fc38970009a460 +Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 From b6bf7cfe0caaf9b00dca586a76597d0e8f88dac7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 23:56:57 -0700 Subject: [PATCH 17/42] push chisel --- chisel | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel b/chisel index 9ceee822..ada8369a 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 9ceee82282839f0dd2d11eb13b59b0a9245944cc +Subproject commit ada8369a39e82890cd78b04db6661f426fb57df2 diff --git a/riscv-tools b/riscv-tools index 85dad284..bc6bbf50 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 85dad28489c39eb0ea2bc4ef3dc86b9fd8f75ca5 +Subproject commit bc6bbf5024bc5297a928b8620ad0364e44d26cfe From e4b56b5d0e2320ac7d2261d0fe60ec1d9fdf09fd Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 15 Mar 2014 15:31:04 -0700 Subject: [PATCH 18/42] generate verilog for rekall --- project/build.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/project/build.scala b/project/build.scala index a6f98650..877c66a4 100644 --- a/project/build.scala +++ b/project/build.scala @@ -31,7 +31,8 @@ object BuildSettings extends Build { lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) + lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") From 7f23257873c8a62c93e4447876457a5772010362 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 17 Mar 2014 15:35:17 -0700 Subject: [PATCH 19/42] Print out random seed if test fails --- csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 6b90d469..f7d73aaa 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -139,7 +139,7 @@ int main(int argc, char** argv) if (htif->exit_code()) { - fprintf(stderr, "*** FAILED *** (code = %d) after %lld cycles\n", htif->exit_code(), (long long)trace_count); + fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %lld cycles\n", htif->exit_code(), random_seed, (long long)trace_count); ret = htif->exit_code(); } else if (trace_count == max_cycles) From 0d124d283a8850061e8e738eddcc67dbb9ee1c73 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 17 Mar 2014 17:02:28 -0700 Subject: [PATCH 20/42] Write our own vcs main() routine --- chisel | 2 +- csrc/vcs_main.cc | 82 ++++++++++++++++++++++-------------------------- 2 files changed, 38 insertions(+), 46 deletions(-) diff --git a/chisel b/chisel index f8c3c094..a2388fee 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit f8c3c094a685c1f5630bd2f61ba0434c2dfbd58f +Subproject commit a2388fee713e67b5b4f490ae203093dd8d9a5d33 diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc index a406a826..9efcd6fb 100644 --- a/csrc/vcs_main.cc +++ b/csrc/vcs_main.cc @@ -8,12 +8,41 @@ #include #include -static htif_emulator_t* htif = NULL; -static unsigned htif_bytes; -static mm_t* mm = NULL; - extern "C" { +extern int vcs_main(int argc, char** argv); + +static htif_emulator_t* htif; +static unsigned htif_bytes; +static mm_t* mm; +static const char* loadmem; + +void htif_fini(int code) +{ + delete htif; + htif = NULL; + exit(code); +} + +int main(int argc, char** argv) +{ + bool dramsim = false; + + for (int i = 1; i < argc; i++) + { + if (!strcmp(argv[i], "+dramsim")) + dramsim = true; + else if (!strncmp(argv[i], "+loadmem=", 9)) + loadmem = argv[i]+9; + } + + mm = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); + htif = new htif_emulator_t(std::vector(argv + 1, argv + argc)); + + vcs_main(argc, argv); + abort(); // should never get here +} + void memory_tick( vc_handle mem_req_val, vc_handle mem_req_rdy, @@ -62,55 +91,18 @@ void memory_tick( ); } -void htif_init -( - vc_handle htif_width, - vc_handle mem_width, - vc_handle argv, - vc_handle loadmem, - vc_handle dramsim -) +void htif_init(vc_handle htif_width, vc_handle mem_width) { int mw = vc_4stVectorRef(mem_width)->d; - mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); assert(mw && (mw & (mw-1)) == 0); mm->init(MEM_SIZE, mw/8, LINE_SIZE); + if (loadmem) + load_mem(mm->get_data(), loadmem); + vec32* w = vc_4stVectorRef(htif_width); assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32 htif_bytes = w->d/8; - - char loadmem_str[1024]; - vc_VectorToString(loadmem, loadmem_str); - if (*loadmem_str) - load_mem(mm->get_data(), loadmem_str); - - char argv_str[1024]; - vc_VectorToString(argv, argv_str); - if (!*argv_str) - { - if (*loadmem_str) - strcpy(argv_str, "none"); - else - { - fprintf(stderr, "Usage: ./simv [host options] +argv=\" [target args]\"\n"); - exit(-1); - } - } - - std::vector args; - std::stringstream ss(argv_str); - std::istream_iterator begin(ss), end; - std::copy(begin, end, std::back_inserter>(args)); - - htif = new htif_emulator_t(args); -} - -void htif_fini(vc_handle failure) -{ - delete htif; - htif = NULL; - exit(vc_getScalar(failure)); } void htif_tick From d2c32b048a2facb667e24962b1f8549315d3f777 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 18 Mar 2014 01:35:08 -0700 Subject: [PATCH 21/42] fix bug in htif_fini, need to use vc_handle! --- csrc/vcs_main.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc index 9efcd6fb..cc9e4a06 100644 --- a/csrc/vcs_main.cc +++ b/csrc/vcs_main.cc @@ -17,11 +17,11 @@ static unsigned htif_bytes; static mm_t* mm; static const char* loadmem; -void htif_fini(int code) +void htif_fini(vc_handle failure) { delete htif; htif = NULL; - exit(code); + exit(vc_getScalar(failure)); } int main(int argc, char** argv) From 51808d998257cef9a82d00b45dd2c8c908a18acf Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 18 Mar 2014 18:37:53 -0700 Subject: [PATCH 22/42] Fix minor FP bugs --- hardfloat | 2 +- riscv-tests | 2 +- rocket | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hardfloat b/hardfloat index 2a05ecbb..8415eba0 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 +Subproject commit 8415eba06ffac9dfa5203bfca9b10afae2316961 diff --git a/riscv-tests b/riscv-tests index ea6edc71..7e146003 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c +Subproject commit 7e1460032cf6f522ce4bc7e8a347c1f08a4476d2 diff --git a/rocket b/rocket index ddb2db3f..09f42649 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815 +Subproject commit 09f426491ec357cdffee10071a4e3c3b8ba779b3 From 16274a84b6afde352a4f9eadcffb32d12a1c5120 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Fri, 21 Mar 2014 16:21:15 -0700 Subject: [PATCH 23/42] update fpga testbench --- chisel | 2 +- hardfloat | 2 +- riscv-tests | 2 +- rocket | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index d151bbef..2f678db2 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit d151bbeff7bd9917415257482e26760d5fdc1166 +Subproject commit 2f678db2c9013b9a6b6e305784b17997d630517a diff --git a/hardfloat b/hardfloat index 8415eba0..2a05ecbb 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 8415eba06ffac9dfa5203bfca9b10afae2316961 +Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 diff --git a/riscv-tests b/riscv-tests index 7e146003..ea6edc71 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 7e1460032cf6f522ce4bc7e8a347c1f08a4476d2 +Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c diff --git a/rocket b/rocket index 489d3b1c..ddb2db3f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 489d3b1cd57bbdcf443247a359214b644c5c1e9f +Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815 From fb8c7d3da55d678270f3e4e1c6c4ce0d8670b782 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 7 Apr 2014 23:49:06 -0700 Subject: [PATCH 24/42] Push rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index ea4b1dfd..96cf6e14 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit ea4b1dfd17ac7e873f59f8c878dd0a214cf4f868 +Subproject commit 96cf6e140bab50c8b1899d61a15ea9b90bb494dd From f643d386720dac17b7b1fe93b3a8d8b793411d88 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 8 Apr 2014 16:50:52 -0700 Subject: [PATCH 25/42] Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required) --- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-tests b/riscv-tests index 629d7edf..8a86a3e4 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 629d7edf826573a9bf297486999e23a7b745c44d +Subproject commit 8a86a3e45d2ca91ea218b92d3e7a1b73d00872e7 diff --git a/riscv-tools b/riscv-tools index bc6bbf50..f6d563db 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit bc6bbf5024bc5297a928b8620ad0364e44d26cfe +Subproject commit f6d563db1fb020bb6fba2db841dbedfbdb3175e8 diff --git a/rocket b/rocket index 96cf6e14..053836a7 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 96cf6e140bab50c8b1899d61a15ea9b90bb494dd +Subproject commit 053836a7b9dbfc036603533413d96a4887504641 From cac04afc258c63528774cdb5da5ad60a430d3a43 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 8 Apr 2014 22:14:16 -0700 Subject: [PATCH 26/42] Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL. --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index 8a86a3e4..8f6e2420 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 8a86a3e45d2ca91ea218b92d3e7a1b73d00872e7 +Subproject commit 8f6e2420926471a7bd9a660305ab3d6a22f22dc9 diff --git a/riscv-tools b/riscv-tools index f6d563db..0b1408b0 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit f6d563db1fb020bb6fba2db841dbedfbdb3175e8 +Subproject commit 0b1408b08f380cea59f7a41d2f5729009af792fc From 5a5f69bfcac0d93e7eb988c39c216b6d4fbd2d4c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 10 Apr 2014 13:13:46 -0700 Subject: [PATCH 27/42] finished uncore constant/tilelink data refactor --- chisel | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 56 ++++++++++++++++++++++++--------- src/main/scala/fpga.scala | 26 ++++++++++----- uncore | 2 +- 5 files changed, 64 insertions(+), 24 deletions(-) diff --git a/chisel b/chisel index 663b8716..41d48485 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 663b8716aa157a6b82f7f4e4f7cbfeb59c9bc3b5 +Subproject commit 41d48485e1cd454e5b7966a6efaac63ba5656796 diff --git a/rocket b/rocket index 47e883ed..5bc618bc 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 47e883edc125488b3354729af2669ec8e4123a8b +Subproject commit 5bc618bc74bf3dffb11f8a6366299c31bf7a247b diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 5c23b074..5a331412 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -8,8 +8,8 @@ import ReferenceChipBackend._ import scala.collection.mutable.HashMap import DRAMModel._ -object DummyTopLevelConstants { - val NTILES = 2 +object DesignSpaceConstants { + val NTILES = 1 val NBANKS = 1 val HTIF_WIDTH = 16 val ENABLE_SHARING = true @@ -18,13 +18,31 @@ object DummyTopLevelConstants { val NL2_REL_XACTS = 1 val NL2_ACQ_XACTS = 7 val NMSHRS = 2 +} + +object MemoryConstants { + val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 //TODO: How configurable is this really? + val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES) + val PADDR_BITS = 32 + val VADDR_BITS = 43 + val PGIDX_BITS = 13 + val ASID_BITS = 7 + val PERM_BITS = 6 val MEM_TAG_BITS = 5 val MEM_DATA_BITS = 128 val MEM_ADDR_BITS = PADDR_BITS - OFFSET_BITS val MEM_DATA_BEATS = 4 } -import DummyTopLevelConstants._ +object TileLinkSizeConstants { + val WRITE_MASK_BITS = 6 + val SUBWORD_ADDR_BITS = 3 + val ATOMIC_OP_BITS = 4 +} + +import DesignSpaceConstants._ +import MemoryConstants._ +import TileLinkSizeConstants._ object ReferenceChipBackend { val initMap = new HashMap[Module, Bool]() @@ -150,7 +168,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext io.mem_backup <> mem_serdes.io.narrow } -case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int) +case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int) class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { @@ -164,7 +182,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module val mem_backup = new MemSerializedIO(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits)) val outmemsys = Module(new OuterMemorySystem(htif_width)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif @@ -250,19 +268,29 @@ class Top extends Module { } implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1) - implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), CACHE_DATA_SIZE_IN_BYTES*8) + implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) + implicit val tl = TileLinkConfiguration(co = co, ln = ln, + addrBits = as.paddrBits-OFFSET_BITS, + clientXactIdBits = log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), + masterXactIdBits = 2*log2Up(NMSHRS*NTILES+1), + dataBits = CACHE_DATA_SIZE_IN_BYTES*8, + writeMaskBits = WRITE_MASK_BITS, + wordAddrBits = SUBWORD_ADDR_BITS, + atomicOpBits = ATOMIC_OP_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) - implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) + implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS) - val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38, tl = tl) - val dc = DCacheConfig(128, 4, ntlb = 8, - nmshr = NMSHRS, nrpq = 16, nsdq = 17, tl = tl) - val vic = ICacheConfig(128, 1, tl = tl) - val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) + val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 8)) + val dc = DCacheConfig(sets = 128, ways = 4, + tl = tl, as = as, + ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, + reqtagbits = -1, databits = -1) + val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) + val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None - val rc = RocketConfiguration(tl, ic, dc, fpu - //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + val rc = RocketConfiguration(tl, as, ic, dc, fpu, + rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) val io = new VLSITopIO(HTIF_WIDTH) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 28aedc33..ae82bc2b 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -47,7 +47,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif @@ -73,6 +73,9 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo htif.io.host.in <> io.host.in } +import MemoryConstants._ +import TileLinkSizeConstants._ + class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extends Module { val io = new Bundle { val host_in = new DecoupledIO(new HostPacket(htif_width)).flip() @@ -90,13 +93,21 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend val nbanks = 1 val nmshrs = 2 implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1) - implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), CACHE_DATA_SIZE_IN_BYTES*8) + implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) + implicit val tl = TileLinkConfiguration(co = co, ln = ln, + addrBits = as.paddrBits-OFFSET_BITS, + clientXactIdBits = log2Up(1+8), + masterXactIdBits = 2*log2Up(2*1+1), + dataBits = CACHE_DATA_SIZE_IN_BYTES*8, + writeMaskBits = WRITE_MASK_BITS, + wordAddrBits = SUBWORD_ADDR_BITS, + atomicOpBits = ATOMIC_OP_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) - implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64) + implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS) - val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4, tl = tl) - val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl) - val rc = RocketConfiguration(tl, ic, dc, fpu = None, + val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8)) + val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1) + val rc = RocketConfiguration(tl, as, ic, dc, fpu = None, fastMulDiv = false) val resetSigs = Vec.fill(uc.nTiles){Bool()} @@ -138,13 +149,14 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend io.mem_resp <> uncore.io.mem.resp } +import MemoryConstants._ class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) class FPGATop extends Module { val htif_width = 16 - implicit val mif = MemoryIFConfiguration(PADDR_BITS - OFFSET_BITS, 128, 5, 4) + implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) val deviceWidth = ROW_WIDTH/mif.dataBits implicit val mc = MemoryControllerConfiguration(deviceWidth, (if(deviceWidth == 4) 0 else log2Up(deviceWidth/4)), mif) diff --git a/uncore b/uncore index 67589ccc..240fdc0e 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 67589ccca64716a9be5ab94d50854a8827431be7 +Subproject commit 240fdc0ef7e0735d1b31eb8b8c21fc11f1446a11 From 691aa4107e6cf41a79113273806d687fe96cf329 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 14 Apr 2014 17:13:57 -0700 Subject: [PATCH 28/42] bump rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 5bc618bc..b185fb81 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 5bc618bc74bf3dffb11f8a6366299c31bf7a247b +Subproject commit b185fb81ce29f75d7848bcc91658f1f2b8de15fd From e4c97e7a57ab2a819a0899c071fd0e5c9095df80 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 14 Apr 2014 21:18:22 -0700 Subject: [PATCH 29/42] push tools/tests --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index 8f6e2420..83ed3f51 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 8f6e2420926471a7bd9a660305ab3d6a22f22dc9 +Subproject commit 83ed3f519de9929b6551b98677047228a8ab4d0c diff --git a/riscv-tools b/riscv-tools index 0b1408b0..1f62b9b6 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 0b1408b08f380cea59f7a41d2f5729009af792fc +Subproject commit 1f62b9b6b6503a6a179f5d7b12d5157437405c83 From 1bf5439f0b0a0b87d61e92eef99bd1659a95db45 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 18 Apr 2014 18:05:30 -0700 Subject: [PATCH 30/42] include new mm test in benchmarks --- Makefrag | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefrag b/Makefrag index 497b04b2..7bcd3e06 100644 --- a/Makefrag +++ b/Makefrag @@ -532,7 +532,7 @@ bmarks = \ qsort.riscv \ towers.riscv \ vvadd.riscv \ - dgemm.riscv \ + mm.riscv \ dhrystone.riscv \ spmv.riscv \ #vec-vvadd.riscv \ From cfd6748318792b01c23a25b554d50cc0ed1dce14 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 21 Apr 2014 17:26:33 -0700 Subject: [PATCH 31/42] patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) --- chisel | 2 +- src/main/scala/fpga.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index 41d48485..60fb4c60 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 41d48485e1cd454e5b7966a6efaac63ba5656796 +Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4 diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index ae82bc2b..79203e40 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -185,9 +185,9 @@ class FPGATop extends Module { referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready referenceChip.DecoupledIOs("host_out").host_ready := Bool(true) - io.host.clk := referenceChip.DebugIOs("host_clk") - io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge") - io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr") + io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0) + io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0) + io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0) //reference chip to dram model connections val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd())) From 2fefbdd453bed9ac66849a9e3a0a98a76dae7575 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 21 Apr 2014 21:36:39 -0700 Subject: [PATCH 32/42] fixes to physical design flow --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index b185fb81..bcd678f1 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b185fb81ce29f75d7848bcc91658f1f2b8de15fd +Subproject commit bcd678f1b0e414d3c0793f10c9acb68f7252ce66 From 83a3cb49998f7bd257b88cc10899f30a0a2a975c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 22 Apr 2014 17:32:39 -0700 Subject: [PATCH 33/42] bump rocket, uncore --- rocket | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index bcd678f1..f67dc690 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit bcd678f1b0e414d3c0793f10c9acb68f7252ce66 +Subproject commit f67dc690e3d18eed3274fadba56459c97fdc08f5 diff --git a/uncore b/uncore index 240fdc0e..2519ad9e 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 240fdc0ef7e0735d1b31eb8b8c21fc11f1446a11 +Subproject commit 2519ad9ef58e3798b351c4c20594946a1e1654a4 From 1e062d1bcdd107f371f1d2d40e7221fabfb5ac67 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 23 Apr 2014 16:27:34 -0700 Subject: [PATCH 34/42] bump rocket, uncore --- rocket | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index f67dc690..1a921d17 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit f67dc690e3d18eed3274fadba56459c97fdc08f5 +Subproject commit 1a921d1760d7861ae60a67b659ec022a79740559 diff --git a/uncore b/uncore index 2519ad9e..f6a4cb6e 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 2519ad9ef58e3798b351c4c20594946a1e1654a4 +Subproject commit f6a4cb6ecfc1854d5100aed72bcb7978ea025c13 From fbf6e443764ffa61b256a432590efb795091af34 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 24 Apr 2014 11:58:59 -0700 Subject: [PATCH 35/42] fix connection error in fpga uncore --- src/main/scala/fpga.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 79203e40..6ecabdaf 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo case ((outer, client), i) => outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) - outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.release, i)) + outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } From 3d4273954af398757942fd9f9cbfb26742ee650c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sat, 26 Apr 2014 15:19:25 -0700 Subject: [PATCH 36/42] TileLinkIO.GrantAck -> TileLinkIO.Finish --- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 114 ++++---------------------------- src/main/scala/network.scala | 4 +- uncore | 2 +- 5 files changed, 19 insertions(+), 105 deletions(-) diff --git a/rocket b/rocket index 1a921d17..23a104b0 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 1a921d1760d7861ae60a67b659ec022a79740559 +Subproject commit 23a104b04472df241ca3074d0adf45c93d3da223 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index a428ab92..cf07125f 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -200,7 +200,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module case ((outer, client), i) => outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) - outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i)) + outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 6ecabdaf..54fc35a2 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo case ((outer, client), i) => outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) - outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i)) + outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } @@ -76,18 +76,17 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo import MemoryConstants._ import TileLinkSizeConstants._ -class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extends Module { - val io = new Bundle { - val host_in = new DecoupledIO(new HostPacket(htif_width)).flip() - val host_out = new DecoupledIO(new HostPacket(htif_width)) - val host_clk = Bool(OUTPUT) - val host_clk_edge = Bool(OUTPUT) - val host_debug_stats_pcr = Bool(OUTPUT) - val mem_req_cmd = new DecoupledIO(new MemReqCmd()) - val mem_req_data = new DecoupledIO(new MemData()) - val mem_resp = (new DecoupledIO(new MemResp())).flip() - } +import MemoryConstants._ + +class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) + +class FPGATop extends Module { + val htif_width = 16 + implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) + + val io = new FPGATopIO(htif_width) + val co = new MESICoherence val ntiles = 1 val nbanks = 1 @@ -131,94 +130,9 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend hl.ipi_req <> Queue(tile.io.host.ipi_req) tile.io.host.ipi_rep <> Queue(hl.ipi_rep) } - - io.host_in.ready := uncore.io.host.in.ready - uncore.io.host.in.bits := io.host_in.bits.data - uncore.io.host.in.valid := io.host_in.valid - - uncore.io.host.out.ready := io.host_out.ready - io.host_out.bits.data := uncore.io.host.out.bits - io.host_out.valid := uncore.io.host.out.valid - - io.host_clk := uncore.io.host.clk - io.host_clk_edge := uncore.io.host.clk_edge - io.host_debug_stats_pcr := uncore.io.host.debug_stats_pcr - - io.mem_req_cmd <> uncore.io.mem.req_cmd - io.mem_req_data <> uncore.io.mem.req_data - io.mem_resp <> uncore.io.mem.resp -} - -import MemoryConstants._ - -class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) - -class FPGATop extends Module { - val htif_width = 16 - - implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) - val deviceWidth = ROW_WIDTH/mif.dataBits - implicit val mc = MemoryControllerConfiguration(deviceWidth, (if(deviceWidth == 4) 0 else log2Up(deviceWidth/4)), mif) - - val io = new FPGATopIO(htif_width) - - val referenceChip = Module(new Fame1Wrapper(new ReferenceChip(htif_width))) - val dramModel = Module(new DRAMSystemWrapper()) - //dram model parameters setup - dramModel.io.params.tRAS := UInt(4) - dramModel.io.params.tRCD := UInt(4) - dramModel.io.params.tRP := UInt(4) - dramModel.io.params.tCCD := UInt(4) - dramModel.io.params.tRTP := UInt(4) - dramModel.io.params.tWTR := UInt(4) - dramModel.io.params.tWR := UInt(4) - dramModel.io.params.tRRD := UInt(4) - - //host to reference chip connections - referenceChip.DecoupledIOs("host_in").host_valid := Bool(true) - referenceChip.DecoupledIOs("host_in").target.bits := io.host.in.bits - referenceChip.DecoupledIOs("host_in").target.valid := io.host.in.valid - io.host.in.ready := referenceChip.DecoupledIOs("host_in").host_ready && referenceChip.DecoupledIOs("host_in").target.ready - - io.host.out.valid := referenceChip.DecoupledIOs("host_out").host_valid && referenceChip.DecoupledIOs("host_out").target.valid - io.host.out.bits := referenceChip.DecoupledIOs("host_out").target.bits - referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready - referenceChip.DecoupledIOs("host_out").host_ready := Bool(true) - - io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0) - io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0) - io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0) - - //reference chip to dram model connections - val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd())) - val mem_req_data_queue = Module(new FameQueue(8)(new MemData())) - val mem_resp_queue = Module(new FameQueue(8)(new MemResp())) - - //cmd queue - FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_cmd"), mem_req_cmd_queue.io.enq, new MemReqCmd) - mem_req_cmd_queue.io.deq <> dramModel.io.memReqCmd - - //data queue - FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_data"), mem_req_data_queue.io.enq, new MemData) - mem_req_data_queue.io.deq <> dramModel.io.memReqData - - //resp queue - mem_resp_queue.io.enq <> dramModel.io.memResp - FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_resp"), mem_resp_queue.io.deq, new MemResp) - - //dram model to outside memory connections - val host_mem_cmd_queue = Module(new Queue(new MemReqCmd, 2)) - val host_mem_data_queue = Module(new Queue(new MemData, mif.dataBeats)) - val host_mem_resp_queue = Module(new Queue(new MemResp, mif.dataBeats)) - - host_mem_cmd_queue.io.enq <> dramModel.io.mem.req_cmd - host_mem_cmd_queue.io.deq <> io.mem.req_cmd - - host_mem_data_queue.io.enq <> dramModel.io.mem.req_data - host_mem_data_queue.io.deq <> io.mem.req_data - - host_mem_resp_queue.io.enq <> io.mem.resp - host_mem_resp_queue.io.deq <> dramModel.io.mem.resp + + uncore.io.host <> io.host + uncore.io.mem <> io.mem } abstract class AXISlave extends Module { diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala index 57d960a1..6670f89a 100644 --- a/src/main/scala/network.scala +++ b/src/main/scala/network.scala @@ -36,7 +36,7 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L val relNet = Module(new BasicCrossbar(new Release)) val prbNet = Module(new BasicCrossbar(new Probe)) val gntNet = Module(new BasicCrossbar(new Grant)) - val ackNet = Module(new BasicCrossbar(new GrantAck)) + val ackNet = Module(new BasicCrossbar(new Finish)) // Aliases for the various network IO bundle types type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] @@ -125,5 +125,5 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release) doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe) doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant) - doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack) + doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.finish) } diff --git a/uncore b/uncore index f6a4cb6e..4ca76eba 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit f6a4cb6ecfc1854d5100aed72bcb7978ea025c13 +Subproject commit 4ca76ebaad5e796121fcb6843b00a6e5da25cd6f From 224e286dd36406da20fde9f29b8e2b1525a0f7e9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sat, 26 Apr 2014 19:16:37 -0700 Subject: [PATCH 37/42] New uncore config objects. Backends get their own file. Simplify fpga uncore. --- rocket | 2 +- src/main/scala/Backends.scala | 69 +++++++++++++++++++++++ src/main/scala/RocketChip.scala | 98 +++++++-------------------------- src/main/scala/fpga.scala | 57 ++++++++----------- src/main/scala/network.scala | 11 ++-- uncore | 2 +- 6 files changed, 118 insertions(+), 121 deletions(-) create mode 100644 src/main/scala/Backends.scala diff --git a/rocket b/rocket index 23a104b0..6a2c51c4 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 23a104b04472df241ca3074d0adf45c93d3da223 +Subproject commit 6a2c51c405a8687f40e229846a27c6cdb788f221 diff --git a/src/main/scala/Backends.scala b/src/main/scala/Backends.scala new file mode 100644 index 00000000..e1157837 --- /dev/null +++ b/src/main/scala/Backends.scala @@ -0,0 +1,69 @@ +package referencechip + +import Chisel._ +import ReferenceChipBackend._ +import scala.collection.mutable.HashMap + +object ReferenceChipBackend { + val initMap = new HashMap[Module, Bool]() +} + +class ReferenceChipBackend extends VerilogBackend +{ + initMap.clear() + override def emitPortDef(m: MemAccess, idx: Int) = { + val res = new StringBuilder() + for (node <- m.mem.inputs) { + if(node.name.contains("init")) + res.append(" .init(" + node.name + "),\n") + } + (if (idx == 0) res.toString else "") + super.emitPortDef(m, idx) + } + + def addMemPin(c: Module) = { + for (mod <- Module.components; node <- mod.nodes) { + if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) { + connectMemPin(c, node.component, node) + } + } + } + + def connectMemPin(topC: Module, c: Module, p: Node): Unit = { + var isNewPin = false + val compInitPin = + if (initMap.contains(c)) { + initMap(c) + } else { + isNewPin = true + val res = Bool(INPUT) + res.isIo = true + res + } + + p.inputs += compInitPin + + if (isNewPin) { + compInitPin.setName("init") + c.io.asInstanceOf[Bundle] += compInitPin + compInitPin.component = c + initMap += (c -> compInitPin) + connectMemPin(topC, c.parent, compInitPin) + } + } + + def addTopLevelPin(c: Module) = { + val init = Bool(INPUT) + init.isIo = true + init.setName("init") + init.component = c + c.io.asInstanceOf[Bundle] += init + initMap += (c -> init) + } + + transforms += ((c: Module) => addTopLevelPin(c)) + transforms += ((c: Module) => addMemPin(c)) + transforms += ((c: Module) => collectNodesIntoComp(initializeDFS)) +} + +class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform + diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index cf07125f..2f9fb09f 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -4,9 +4,6 @@ import Chisel._ import uncore._ import rocket._ import rocket.Util._ -import ReferenceChipBackend._ -import scala.collection.mutable.HashMap -import DRAMModel._ object DesignSpaceConstants { val NTILES = 1 @@ -44,69 +41,6 @@ import DesignSpaceConstants._ import MemoryConstants._ import TileLinkSizeConstants._ -object ReferenceChipBackend { - val initMap = new HashMap[Module, Bool]() -} - -class ReferenceChipBackend extends VerilogBackend -{ - initMap.clear() - override def emitPortDef(m: MemAccess, idx: Int) = { - val res = new StringBuilder() - for (node <- m.mem.inputs) { - if(node.name.contains("init")) - res.append(" .init(" + node.name + "),\n") - } - (if (idx == 0) res.toString else "") + super.emitPortDef(m, idx) - } - - def addMemPin(c: Module) = { - for (mod <- Module.components; node <- mod.nodes) { - if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) { - connectMemPin(c, node.component, node) - } - } - } - - def connectMemPin(topC: Module, c: Module, p: Node): Unit = { - var isNewPin = false - val compInitPin = - if (initMap.contains(c)) { - initMap(c) - } else { - isNewPin = true - val res = Bool(INPUT) - res.isIo = true - res - } - - p.inputs += compInitPin - - if (isNewPin) { - compInitPin.setName("init") - c.io.asInstanceOf[Bundle] += compInitPin - compInitPin.component = c - initMap += (c -> compInitPin) - connectMemPin(topC, c.parent, compInitPin) - } - } - - def addTopLevelPin(c: Module) = { - val init = Bool(INPUT) - init.isIo = true - init.setName("init") - init.component = c - c.io.asInstanceOf[Bundle] += init - initMap += (c -> init) - } - - transforms += ((c: Module) => addTopLevelPin(c)) - transforms += ((c: Module) => addMemPin(c)) - transforms += ((c: Module) => collectNodesIntoComp(initializeDFS)) -} - -class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform - class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif) @@ -120,13 +54,19 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext } val refill_cycles = tl.dataBits/mif.dataBits - val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true) - val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true) - val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf)) - //val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, refill_cycles)) - val mem_serdes = Module(new MemSerdes(htif_width)) + val (llc, masterEndpoints) = if(conf.useDRAMSideLLC) { + val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true) + val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true) + val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, + refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf)) + val mes = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) + (llc, mes) + } else { + val llc = Module(new DRAMSideLLCNull(16, refill_cycles)) + val mes = (0 until ln.nMasters).map(i => Module(new L2HellaCache(i))) + (llc, mes) + } - val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } @@ -145,6 +85,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext conv.io.mem.resp <> llc.io.cpu.resp // mux between main and backup memory ports + val mem_serdes = Module(new MemSerdes(htif_width)) val mem_cmdq = Module(new Queue(new MemReqCmd, 2)) mem_cmdq.io.enq <> llc.io.mem.req_cmd mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready) @@ -168,7 +109,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext io.mem_backup <> mem_serdes.io.narrow } -case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int) +case class UncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int, useDRAMSideLLC: Boolean) class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { @@ -200,7 +141,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module case ((outer, client), i) => outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) - outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i)) + outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } @@ -277,9 +218,9 @@ class Top extends Module { writeMaskBits = WRITE_MASK_BITS, wordAddrBits = SUBWORD_ADDR_BITS, atomicOpBits = ATOMIC_OP_BITS) - implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) + implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as) implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) - implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS) + implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = true) val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2)) val dc = DCacheConfig(sets = 128, ways = 4, @@ -306,11 +247,12 @@ class Top extends Module { resetSigs(i) := hl.reset val tile = tileList(i) + tile.io.tilelink <> tl il := hl.reset + tile.io.host.id := UInt(i) tile.io.host.reset := Reg(next=Reg(next=hl.reset)) tile.io.host.pcr_req <> Queue(hl.pcr_req, 1) - tile.io.host.id := i hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1) hl.ipi_req <> Queue(tile.io.host.ipi_req, 1) tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1) @@ -327,5 +269,3 @@ class Top extends Module { io.mem_backup_en <> uncore.io.mem_backup_en io.mem <> uncore.io.mem } - - diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 54fc35a2..fcb17943 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -1,14 +1,13 @@ package referencechip import Chisel._ -import Node._ import uncore._ import rocket._ import DRAMModel._ import DRAMModel.MemModelConstants._ -class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module -{ +class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) + extends Module { implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif) val io = new Bundle { val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip @@ -17,28 +16,23 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) val mem = new MemIO } - val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) - + val master = Module(new L2CoherenceAgent(0)) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } - net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } - masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } + net.io.masters.head <> master.io.client + master.io.incoherent zip io.incoherent map { case (m, c) => m := c } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) - if(ln.nMasters > 1) { - val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)) - arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } - conv.io.uncached <> arb.io.out - } else { - conv.io.uncached <> masterEndpoints.head.io.master - } - io.mem.req_cmd <> Queue(conv.io.mem.req_cmd) + conv.io.uncached <> master.io.master + io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2) io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits) conv.io.mem.resp <> Queue(io.mem.resp) } -class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module -{ +case class FPGAUncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nSCR: Int, offsetBits: Int) + +class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) + extends Module { implicit val (tl, ln, mif) = (conf.tl, conf.tl.ln, conf.mif) val io = new Bundle { val host = new HostIO(htif_width) @@ -55,16 +49,11 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo outmemsys.io.mem <> io.mem // Add networking headers and endpoint queues - def convertAddrToBank(addr: Bits): UInt = { - require(conf.bankIdLsb + log2Up(conf.nBanks) < conf.mif.addrBits, {println("Invalid bits for bank multiplexing.")}) - addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb) - } - (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { case ((outer, client), i) => - outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) - outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) - outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i)) + outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false)) + outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false)) + outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } @@ -81,17 +70,12 @@ import MemoryConstants._ class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) class FPGATop extends Module { + val ntiles = 1 + val nmshrs = 2 val htif_width = 16 - implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) - - val io = new FPGATopIO(htif_width) - val co = new MESICoherence - val ntiles = 1 - val nbanks = 1 - val nmshrs = 2 - implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1) + implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) implicit val tl = TileLinkConfiguration(co = co, ln = ln, addrBits = as.paddrBits-OFFSET_BITS, @@ -102,13 +86,16 @@ class FPGATop extends Module { wordAddrBits = SUBWORD_ADDR_BITS, atomicOpBits = ATOMIC_OP_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) - implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS) + implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) + implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS) - val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8)) + val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2)) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1) val rc = RocketConfiguration(tl, as, ic, dc, fpu = None, fastMulDiv = false) + val io = new FPGATopIO(htif_width) + val resetSigs = Vec.fill(uc.nTiles){Bool()} val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val uncore = Module(new FPGAUncore(htif_width)) diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala index 6670f89a..5deda918 100644 --- a/src/main/scala/network.scala +++ b/src/main/scala/network.scala @@ -6,24 +6,25 @@ import scala.reflect._ import scala.reflect.runtime.universe._ object TileLinkHeaderOverwriter { - def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = { + def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = { val out = in.clone.asDirectionless out.bits.payload := in.bits.payload out.bits.header.src := UInt(clientId) - out.bits.header.dst := in.bits.header.dst + out.bits.header.dst := (if(passThrough) in.bits.header.dst else UInt(0)) out.valid := in.valid in.ready := out.ready out } def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = { - val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId) + val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false) out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0)) out } } -class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) { - implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co) +class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) + extends LogicalNetwork[TileLinkIO]()(conf.ln) { + implicit val (ln, co) = (conf.ln, conf.co) val io = new Bundle { val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip} val masters = Vec.fill(ln.nMasters){new TileLinkIO} diff --git a/uncore b/uncore index 4ca76eba..181a3596 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 4ca76ebaad5e796121fcb6843b00a6e5da25cd6f +Subproject commit 181a35962b3ed19f8687551568300a0a4039eb11 From ce056b4b89b41e1ac338cc4f230d2350aea6badc Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 29 Apr 2014 16:50:07 -0700 Subject: [PATCH 38/42] client/master -> inner/outer --- src/main/scala/RocketChip.scala | 6 +++--- src/main/scala/fpga.scala | 4 ++-- uncore | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 2f9fb09f..4ea2dfe4 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -69,16 +69,16 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } - net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } + net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) if(ln.nMasters > 1) { val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)) - arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } + arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache } conv.io.uncached <> arb.io.out } else { - conv.io.uncached <> masterEndpoints.head.io.master + conv.io.uncached <> masterEndpoints.head.io.outer } llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd) llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index fcb17943..5312a4a3 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -19,11 +19,11 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfigurat val master = Module(new L2CoherenceAgent(0)) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } - net.io.masters.head <> master.io.client + net.io.masters.head <> master.io.inner master.io.incoherent zip io.incoherent map { case (m, c) => m := c } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) - conv.io.uncached <> master.io.master + conv.io.uncached <> master.io.outer io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2) io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits) conv.io.mem.resp <> Queue(io.mem.resp) diff --git a/uncore b/uncore index 181a3596..01aca664 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 181a35962b3ed19f8687551568300a0a4039eb11 +Subproject commit 01aca66442c06ef48438268ed7c97561ecd2cc4e From 445d4f2eee39f78872a2e4e994ef84756257985f Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 1 May 2014 01:46:55 -0700 Subject: [PATCH 39/42] bump rocket, uncore --- rocket | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index 6a2c51c4..7770f07c 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 6a2c51c405a8687f40e229846a27c6cdb788f221 +Subproject commit 7770f07c36b918447b32cb6a1bfe9162aace4c2d diff --git a/uncore b/uncore index 01aca664..48b99169 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 01aca66442c06ef48438268ed7c97561ecd2cc4e +Subproject commit 48b991696e6a674e02be54972d193498dfe76f35 From f8b3117ac01285f6f7e322638c2e868c289ac975 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 6 May 2014 13:10:12 -0700 Subject: [PATCH 40/42] bump rocket, uncore --- rocket | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index 7770f07c..0a58129f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 7770f07c36b918447b32cb6a1bfe9162aace4c2d +Subproject commit 0a58129f59d70d2650f81a889b79996b81d775ab diff --git a/uncore b/uncore index 48b99169..17cb1806 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 48b991696e6a674e02be54972d193498dfe76f35 +Subproject commit 17cb1806c4688f97342dd001ea2e4c54c2c1153f From b0ccb889829ffc4f27291d64fb67b0cc7b669825 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 6 May 2014 13:11:41 -0700 Subject: [PATCH 41/42] make outer cache type choice a top-level const --- src/main/scala/RocketChip.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 4ea2dfe4..0817c63e 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -11,6 +11,7 @@ object DesignSpaceConstants { val HTIF_WIDTH = 16 val ENABLE_SHARING = true val ENABLE_CLEAN_EXCLUSIVE = true + val USE_DRAMSIDE_LLC = true val HAS_FPU = true val NL2_REL_XACTS = 1 val NL2_ACQ_XACTS = 7 @@ -220,7 +221,7 @@ class Top extends Module { atomicOpBits = ATOMIC_OP_BITS) implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as) implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) - implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = true) + implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = USE_DRAMSIDE_LLC) val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2)) val dc = DCacheConfig(sets = 128, ways = 4, From 434da222837df4b0b6a47281290ad160bfd16ec6 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 28 May 2014 14:45:41 -0700 Subject: [PATCH 42/42] Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) --- chisel | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 9 +++++---- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/chisel b/chisel index 60fb4c60..54ad639f 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4 +Subproject commit 54ad639f11a6ac3459dad4d81e007b3712bd66ba diff --git a/rocket b/rocket index 0a58129f..fd9bea86 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 0a58129f59d70d2650f81a889b79996b81d775ab +Subproject commit fd9bea861cf8cb83ff57c419f8a20964742baba5 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 0817c63e..c22a8eb7 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -201,12 +201,13 @@ class MemDessert extends Module { class Top extends Module { + val dir = new FullRepresentation(NTILES+1) val co = if(ENABLE_SHARING) { - if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence - else new MSICoherence + if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir) + else new MSICoherence(dir) } else { - if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence - else new MICoherence + if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir) + else new MICoherence(dir) } implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 5312a4a3..7f4df49b 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -74,7 +74,7 @@ class FPGATop extends Module { val nmshrs = 2 val htif_width = 16 - val co = new MESICoherence + val co = new MESICoherence(new FullRepresentation(ntiles+1)) implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) implicit val tl = TileLinkConfiguration(co = co, ln = ln, diff --git a/uncore b/uncore index 17cb1806..ebe0f493 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 17cb1806c4688f97342dd001ea2e4c54c2c1153f +Subproject commit ebe0f493a62641a71caec9f2959a4f57e2c16b4e