hook up the vector command queue
This commit is contained in:
Yunsup Lee
parent
8b6b0f5367
commit
fcc8081c4d
@ -65,6 +65,7 @@ object Constants
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val WB_ALU = UFix(2, 3);
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val WB_ALU = UFix(2, 3);
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val WB_TSC = UFix(4, 3);
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val WB_TSC = UFix(4, 3);
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val WB_IRT = UFix(5, 3);
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val WB_IRT = UFix(5, 3);
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val WB_VEC = UFix(6, 3);
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val N = UFix(0, 1);
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val N = UFix(0, 1);
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val Y = UFix(1, 1);
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val Y = UFix(1, 1);
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@ -146,8 +147,8 @@ object Constants
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val PCR_K1 = UFix(13, 5);
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val PCR_K1 = UFix(13, 5);
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val PCR_TOHOST = UFix(16, 5);
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val PCR_TOHOST = UFix(16, 5);
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val PCR_FROMHOST = UFix(17, 5);
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val PCR_FROMHOST = UFix(17, 5);
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val PCR_CONSOLE = UFix(18, 5);
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val PCR_VECBANK = UFix(18, 5);
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val PCR_CONSOLE = UFix(19, 5);
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// definition of bits in PCR status reg
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// definition of bits in PCR status reg
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val SR_ET = 0; // enable traps
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val SR_ET = 0; // enable traps
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@ -222,10 +223,9 @@ object Constants
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val VCMD_MF = UFix(5, 3)
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val VCMD_MF = UFix(5, 3)
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val VCMD_X = UFix(0, 3)
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val VCMD_X = UFix(0, 3)
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val VIMM_VLEN = UFix(0, 2)
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val VIMM_VLEN = UFix(0, 1)
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val VIMM_ALU = UFix(1, 2)
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val VIMM_ALU = UFix(1, 1)
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val VIMM_RS1 = UFix(2, 2)
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val VIMM_X = UFix(0, 1)
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val VIMM_X = UFix(0, 2)
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}
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}
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}
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}
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@ -129,11 +129,8 @@ class rocketProc extends Component
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{
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{
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val vu = new vu()
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val vu = new vu()
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vu.io.vec_cmdq <> ctrl.io.vcmdq
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vu.io.vec_cmdq <> dpath.io.vcmdq
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vu.io.vec_cmdq <> dpath.io.vcmdq
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vu.io.vec_ximm1q <> ctrl.io.vximm1q
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vu.io.vec_ximm1q <> dpath.io.vximm1q
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vu.io.vec_ximm1q <> dpath.io.vximm1q
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vu.io.vec_ximm2q <> ctrl.io.vximm2q
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vu.io.vec_ximm2q <> dpath.io.vximm2q
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vu.io.vec_ximm2q <> dpath.io.vximm2q
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}
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}
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}
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}
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@ -80,9 +80,6 @@ class ioCtrlAll extends Bundle()
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val imem = new ioImem(List("req_val", "resp_val")).flip();
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val imem = new ioImem(List("req_val", "resp_val")).flip();
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val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
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val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
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val ext_mem = new ioDmem(List("req_val", "req_cmd", "req_type", "resp_nack"))
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val ext_mem = new ioDmem(List("req_val", "req_cmd", "req_type", "resp_nack"))
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val vcmdq = new io_vec_cmdq(List("ready", "valid"))
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val vximm1q = new io_vec_ximm1q(List("ready", "valid"))
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val vximm2q = new io_vec_ximm2q(List("ready", "valid"))
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val dtlb_val = Bool(OUTPUT);
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val dtlb_val = Bool(OUTPUT);
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val dtlb_kill = Bool(OUTPUT);
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val dtlb_kill = Bool(OUTPUT);
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val dtlb_rdy = Bool(INPUT);
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val dtlb_rdy = Bool(INPUT);
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@ -105,182 +102,170 @@ class rocketCtrl extends Component
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val xpr64 = Y;
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val xpr64 = Y;
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val cs =
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val cs =
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ListLookup(io.dpath.inst,
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ListLookup(io.dpath.inst,
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// eret
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// eret
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// | syscall
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// | syscall
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// mem_val mul_val div_val renpcr | | privileged
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// vec_val mem_val mul_val div_val renpcr | | privileged
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// val brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | replay_next
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// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | | |
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// | | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),Array(
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List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),Array(
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BNE-> List(Y, BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BNE-> List(Y, N,BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BEQ-> List(Y, BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BEQ-> List(Y, N,BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLT-> List(Y, BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLT-> List(Y, N,BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLTU-> List(Y, BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLTU-> List(Y, N,BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGE-> List(Y, BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGE-> List(Y, N,BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGEU-> List(Y, BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGEU-> List(Y, N,BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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J-> List(Y, BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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J-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JAL-> List(Y, BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JAL-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_C-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_C-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_J-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_J-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_R-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_R-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDNPC-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LB-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LH-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LW-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LD-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LD-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LBU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LBU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LHU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LHU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LWU-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LWU-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SB-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SH-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SW-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SW-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SD-> List(xpr64,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SD-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_D-> List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_D->List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_D-> List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_D-> List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_D-> List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_D->List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_D-> List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_D->List(xpr64,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LUI-> List(Y, BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LUI-> List(Y, N,BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTI -> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTI -> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTIU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTIU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ANDI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ANDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ORI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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XORI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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XORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLI-> List(Y_SH, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAI-> List(Y_SH, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADD-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADD-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUB-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLT-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLT-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTU-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvAND-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvAND-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
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riscvOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvXOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvXOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
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SLL-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRL-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRA-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRA-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
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|
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ADDIW-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SLLIW-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRLIW-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRAIW-> List(xpr64,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
ADDW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUBW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUBW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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||||||
MUL-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MUL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MULH-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MULH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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||||||
MULHU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MULHU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
MULHSU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU,N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MULHSU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU,N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
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MULW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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MULW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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|
||||||
DIV-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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DIV-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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DIVU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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DIVU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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||||||
REM-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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REM-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
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REMU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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REMU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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||||||
DIVW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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DIVW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
DIVUW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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DIVUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REMW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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REMW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REMUW-> List(xpr64,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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REMUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SYSCALL-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,N),
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SYSCALL-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,N),
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||||||
EI-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,Y,Y),
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EI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,Y,Y),
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DI-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,Y,Y),
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DI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,Y,Y),
|
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ERET-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,Y,N,Y,N),
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ERET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,Y,N,Y,N),
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FENCE-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N),
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FENCE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N),
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FENCE_I-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N),
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FENCE_I-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N),
|
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CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,Y),
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CFLUSH-> List(Y, N,BR_N, REN_Y,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,Y),
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MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y,N),
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MFPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y,N),
|
||||||
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y,Y),
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MTPCR-> List(Y, N,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y,Y),
|
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RDTIME-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDTIME-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
RDCYCLE-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDCYCLE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
RDINSTRET->List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
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|
||||||
// Instructions that have not yet been implemented
|
// Instructions that have not yet been implemented
|
||||||
// Faking these for now so akaros will boot
|
// Faking these for now so akaros will boot
|
||||||
//MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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//MFFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
//MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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//MTFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FLW-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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FLW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FLD-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
FLD-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FSW-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
FSW-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FSD-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
|
FSD-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
|
// Vector Stuff
|
||||||
|
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_VEC,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y),
|
||||||
|
VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_VEC,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y),
|
||||||
|
VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VMSV-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
FENCE_L_V-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
FENCE_G_V-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
FENCE_L_CV->List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
FENCE_G_CV->List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLWU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLHU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLBU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTWU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTHU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VLSTBU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VSSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
|
||||||
|
VFSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N)
|
||||||
))
|
))
|
||||||
|
|
||||||
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
|
val id_int_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
|
||||||
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
|
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
|
||||||
val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
|
val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
|
||||||
|
|
||||||
val veccs =
|
|
||||||
ListLookup(io.dpath.inst,
|
|
||||||
// appvlmask
|
|
||||||
// | vcmdq
|
|
||||||
// | | vximm1q
|
|
||||||
// | | | vximm2q
|
|
||||||
// val ren2 ren1 vcmd vimm fn | | | | vackq
|
|
||||||
// | | | | | | | | | | |
|
|
||||||
List(N,REN_N,REN_N,VCMD_X, VIMM_X, VEC_X ,N,N,N,N,N),Array(
|
|
||||||
VVCFGIVL-> List(Y,REN_N,REN_Y,VCMD_I, VIMM_VLEN,VEC_CFG,N,Y,Y,N,N),
|
|
||||||
VSETVL-> List(Y,REN_N,REN_Y,VCMD_I, VIMM_VLEN,VEC_VL ,N,Y,Y,N,N),
|
|
||||||
VF-> List(Y,REN_Y,REN_Y,VCMD_I, VIMM_ALU, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VMVV-> List(Y,REN_N,REN_N,VCMD_TX,VIMM_X, VEC_X ,Y,Y,N,N,N),
|
|
||||||
VMSV-> List(Y,REN_N,REN_Y,VCMD_TX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VFMVV-> List(Y,REN_N,REN_N,VCMD_TF,VIMM_X, VEC_X ,Y,Y,N,N,N),
|
|
||||||
FENCE_L_V-> List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,N),
|
|
||||||
FENCE_G_V-> List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,N),
|
|
||||||
FENCE_L_CV->List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,Y),
|
|
||||||
FENCE_G_CV->List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,Y),
|
|
||||||
VLD-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLW-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLWU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLH-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLHU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLB-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLBU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VSD-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VSW-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VSH-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VSB-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VFLD-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VFLW-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VFSD-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VFSW-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
|
|
||||||
VLSTD-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTW-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTWU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTH-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTHU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTB-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VLSTBU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VSSTD-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VSSTW-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VSSTH-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VSSTB-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VFLSTD-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VFLSTW-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VFSSTD-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
|
|
||||||
VFSSTW-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N)
|
|
||||||
))
|
|
||||||
|
|
||||||
val id_vec_val :: id_renv2 :: id_renv1 :: id_sel_vcmd :: id_sel_vimm :: id_fn_vec :: id_vec_appvlmask :: veccs0 = veccs
|
|
||||||
val id_vec_cmdq_val :: id_vec_ximm1q_val :: id_vec_ximm2q_val :: id_vec_ackq_wait :: Nil = veccs0
|
|
||||||
|
|
||||||
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
|
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
|
||||||
|
|
||||||
val id_raddr3 = io.dpath.inst(16,12);
|
val id_raddr3 = io.dpath.inst(16,12);
|
||||||
@ -320,6 +305,7 @@ class rocketCtrl extends Component
|
|||||||
val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
|
val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
|
val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_fp_val = Reg(resetVal = Bool(false));
|
val ex_reg_fp_val = Reg(resetVal = Bool(false));
|
||||||
|
val ex_reg_vec_val = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_replay = Reg(resetVal = Bool(false));
|
val ex_reg_replay = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_load_use = Reg(resetVal = Bool(false));
|
val ex_reg_load_use = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_ext_mem_val = Reg(resetVal = Bool(false))
|
val ex_reg_ext_mem_val = Reg(resetVal = Bool(false))
|
||||||
@ -334,6 +320,7 @@ class rocketCtrl extends Component
|
|||||||
val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
|
val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
|
val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
|
val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
|
||||||
|
val mem_reg_xcpt_vec = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
|
val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_replay = Reg(resetVal = Bool(false));
|
val mem_reg_replay = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_kill = Reg(resetVal = Bool(false));
|
val mem_reg_kill = Reg(resetVal = Bool(false));
|
||||||
@ -367,7 +354,9 @@ class rocketCtrl extends Component
|
|||||||
}
|
}
|
||||||
|
|
||||||
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
|
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
|
||||||
val illegal_inst = !(id_int_val.toBool || fpdec.io.valid) || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
|
val illegal_inst =
|
||||||
|
!(id_int_val.toBool || fpdec.io.valid || id_vec_val.toBool) ||
|
||||||
|
(id_eret.toBool && io.dpath.status(SR_ET).toBool);
|
||||||
|
|
||||||
when (reset.toBool || io.dpath.killd) {
|
when (reset.toBool || io.dpath.killd) {
|
||||||
ex_reg_br_type <== BR_N;
|
ex_reg_br_type <== BR_N;
|
||||||
@ -388,6 +377,7 @@ class rocketCtrl extends Component
|
|||||||
ex_reg_xcpt_privileged <== Bool(false);
|
ex_reg_xcpt_privileged <== Bool(false);
|
||||||
ex_reg_xcpt_syscall <== Bool(false);
|
ex_reg_xcpt_syscall <== Bool(false);
|
||||||
ex_reg_fp_val <== Bool(false);
|
ex_reg_fp_val <== Bool(false);
|
||||||
|
ex_reg_vec_val <== Bool(false);
|
||||||
ex_reg_replay <== Bool(false);
|
ex_reg_replay <== Bool(false);
|
||||||
ex_reg_load_use <== Bool(false);
|
ex_reg_load_use <== Bool(false);
|
||||||
}
|
}
|
||||||
@ -410,6 +400,7 @@ class rocketCtrl extends Component
|
|||||||
ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool;
|
ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool;
|
||||||
ex_reg_xcpt_syscall <== id_syscall.toBool;
|
ex_reg_xcpt_syscall <== id_syscall.toBool;
|
||||||
ex_reg_fp_val <== fpdec.io.valid;
|
ex_reg_fp_val <== fpdec.io.valid;
|
||||||
|
ex_reg_vec_val <== id_vec_val.toBool
|
||||||
ex_reg_replay <== id_reg_replay || ex_reg_replay_next;
|
ex_reg_replay <== id_reg_replay || ex_reg_replay_next;
|
||||||
ex_reg_load_use <== id_load_use;
|
ex_reg_load_use <== id_load_use;
|
||||||
}
|
}
|
||||||
@ -454,6 +445,7 @@ class rocketCtrl extends Component
|
|||||||
mem_reg_xcpt_illegal <== Bool(false);
|
mem_reg_xcpt_illegal <== Bool(false);
|
||||||
mem_reg_xcpt_privileged <== Bool(false);
|
mem_reg_xcpt_privileged <== Bool(false);
|
||||||
mem_reg_xcpt_fpu <== Bool(false);
|
mem_reg_xcpt_fpu <== Bool(false);
|
||||||
|
mem_reg_xcpt_vec <== Bool(false);
|
||||||
mem_reg_xcpt_syscall <== Bool(false);
|
mem_reg_xcpt_syscall <== Bool(false);
|
||||||
}
|
}
|
||||||
otherwise {
|
otherwise {
|
||||||
@ -470,6 +462,7 @@ class rocketCtrl extends Component
|
|||||||
mem_reg_xcpt_illegal <== ex_reg_xcpt_illegal;
|
mem_reg_xcpt_illegal <== ex_reg_xcpt_illegal;
|
||||||
mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
|
mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
|
||||||
mem_reg_xcpt_fpu <== ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
|
mem_reg_xcpt_fpu <== ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
|
||||||
|
mem_reg_xcpt_vec <== ex_reg_vec_val && !io.dpath.status(SR_EV).toBool;
|
||||||
mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
|
mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
|
||||||
}
|
}
|
||||||
mem_reg_ext_mem_val <== ex_reg_ext_mem_val;
|
mem_reg_ext_mem_val <== ex_reg_ext_mem_val;
|
||||||
@ -559,6 +552,7 @@ class rocketCtrl extends Component
|
|||||||
mem_reg_xcpt_illegal ||
|
mem_reg_xcpt_illegal ||
|
||||||
mem_reg_xcpt_privileged ||
|
mem_reg_xcpt_privileged ||
|
||||||
mem_reg_xcpt_fpu ||
|
mem_reg_xcpt_fpu ||
|
||||||
|
mem_reg_xcpt_vec ||
|
||||||
mem_reg_xcpt_syscall ||
|
mem_reg_xcpt_syscall ||
|
||||||
mem_reg_xcpt_itlb ||
|
mem_reg_xcpt_itlb ||
|
||||||
mem_reg_xcpt_ma_inst;
|
mem_reg_xcpt_ma_inst;
|
||||||
@ -575,7 +569,8 @@ class rocketCtrl extends Component
|
|||||||
Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
|
Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
|
||||||
Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
|
Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
|
||||||
Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
|
Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
|
||||||
UFix(0,5))))))))))); // instruction address misaligned
|
Mux(mem_reg_xcpt_vec, UFix(12,5), // vector disabled
|
||||||
|
UFix(0,5)))))))))))); // instruction address misaligned
|
||||||
|
|
||||||
// control transfer from ex/mem
|
// control transfer from ex/mem
|
||||||
val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
|
val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
|
||||||
|
|||||||
@ -33,11 +33,11 @@ class ioDpathAll extends Bundle()
|
|||||||
val console = new ioConsole(List("valid","bits"));
|
val console = new ioConsole(List("valid","bits"));
|
||||||
val debug = new ioDebug();
|
val debug = new ioDebug();
|
||||||
val dmem = new ioDpathDmem();
|
val dmem = new ioDpathDmem();
|
||||||
val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "resp_val", "resp_data", "resp_tag"))
|
val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "resp_val", "resp_data", "resp_tag"))
|
||||||
val imem = new ioDpathImem();
|
val imem = new ioDpathImem();
|
||||||
val vcmdq = new io_vec_cmdq(List("bits"))
|
val vcmdq = new io_vec_cmdq()
|
||||||
val vximm1q = new io_vec_ximm1q(List("bits"))
|
val vximm1q = new io_vec_ximm1q()
|
||||||
val vximm2q = new io_vec_ximm2q(List("bits"))
|
val vximm2q = new io_vec_ximm2q()
|
||||||
val ptbr_wen = Bool(OUTPUT);
|
val ptbr_wen = Bool(OUTPUT);
|
||||||
val ptbr = UFix(PADDR_BITS, OUTPUT);
|
val ptbr = UFix(PADDR_BITS, OUTPUT);
|
||||||
val fpu = new ioDpathFPU();
|
val fpu = new ioDpathFPU();
|
||||||
@ -54,6 +54,8 @@ class rocketDpath extends Component
|
|||||||
val pcr = new rocketDpathPCR();
|
val pcr = new rocketDpathPCR();
|
||||||
val ex_pcr = pcr.io.r.data;
|
val ex_pcr = pcr.io.r.data;
|
||||||
|
|
||||||
|
val vec = new rocketDpathVec()
|
||||||
|
|
||||||
val alu = new rocketDpathALU();
|
val alu = new rocketDpathALU();
|
||||||
val ex_alu_out = alu.io.out;
|
val ex_alu_out = alu.io.out;
|
||||||
val ex_alu_adder_out = alu.io.adder_out;
|
val ex_alu_adder_out = alu.io.adder_out;
|
||||||
@ -81,6 +83,8 @@ class rocketDpath extends Component
|
|||||||
// execute definitions
|
// execute definitions
|
||||||
val ex_reg_valid = Reg(resetVal = Bool(false));
|
val ex_reg_valid = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_pc = Reg() { UFix() };
|
val ex_reg_pc = Reg() { UFix() };
|
||||||
|
val ex_reg_inst = Reg() { Bits() };
|
||||||
|
val ex_reg_raddr1 = Reg() { UFix() };
|
||||||
val ex_reg_raddr2 = Reg() { UFix() };
|
val ex_reg_raddr2 = Reg() { UFix() };
|
||||||
val ex_reg_op2 = Reg() { Bits() };
|
val ex_reg_op2 = Reg() { Bits() };
|
||||||
val ex_reg_rs2 = Reg() { Bits() };
|
val ex_reg_rs2 = Reg() { Bits() };
|
||||||
@ -101,8 +105,11 @@ class rocketDpath extends Component
|
|||||||
// memory definitions
|
// memory definitions
|
||||||
val mem_reg_valid = Reg(resetVal = Bool(false));
|
val mem_reg_valid = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_pc = Reg() { UFix() };
|
val mem_reg_pc = Reg() { UFix() };
|
||||||
|
val mem_reg_inst = Reg() { Bits() };
|
||||||
|
val mem_reg_rs2 = Reg() { Bits() };
|
||||||
val mem_reg_waddr = Reg() { UFix() };
|
val mem_reg_waddr = Reg() { UFix() };
|
||||||
val mem_reg_wdata = Reg() { Bits() };
|
val mem_reg_wdata = Reg() { Bits() };
|
||||||
|
val mem_reg_raddr1 = Reg() { UFix() };
|
||||||
val mem_reg_raddr2 = Reg() { UFix() };
|
val mem_reg_raddr2 = Reg() { UFix() };
|
||||||
val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
|
val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
|
||||||
val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
|
val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
|
||||||
@ -112,8 +119,11 @@ class rocketDpath extends Component
|
|||||||
// writeback definitions
|
// writeback definitions
|
||||||
val wb_reg_valid = Reg(resetVal = Bool(false));
|
val wb_reg_valid = Reg(resetVal = Bool(false));
|
||||||
val wb_reg_pc = Reg() { UFix() };
|
val wb_reg_pc = Reg() { UFix() };
|
||||||
|
val wb_reg_inst = Reg() { Bits() };
|
||||||
|
val wb_reg_rs2 = Reg() { Bits() };
|
||||||
val wb_reg_waddr = Reg() { UFix() };
|
val wb_reg_waddr = Reg() { UFix() };
|
||||||
val wb_reg_wdata = Reg() { Bits() };
|
val wb_reg_wdata = Reg() { Bits() };
|
||||||
|
val wb_reg_raddr1 = Reg() { UFix() };
|
||||||
val wb_reg_raddr2 = Reg() { UFix() };
|
val wb_reg_raddr2 = Reg() { UFix() };
|
||||||
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
|
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
|
||||||
val wb_reg_ll_wb = Reg(resetVal = Bool(false));
|
val wb_reg_ll_wb = Reg(resetVal = Bool(false));
|
||||||
@ -230,6 +240,8 @@ class rocketDpath extends Component
|
|||||||
|
|
||||||
// execute stage
|
// execute stage
|
||||||
ex_reg_pc <== id_reg_pc;
|
ex_reg_pc <== id_reg_pc;
|
||||||
|
ex_reg_inst <== id_reg_inst
|
||||||
|
ex_reg_raddr1 <== id_raddr1
|
||||||
ex_reg_raddr2 <== id_raddr2;
|
ex_reg_raddr2 <== id_raddr2;
|
||||||
ex_reg_op2 <== id_op2;
|
ex_reg_op2 <== id_op2;
|
||||||
ex_reg_rs2 <== id_rs2;
|
ex_reg_rs2 <== id_rs2;
|
||||||
@ -333,16 +345,20 @@ class rocketDpath extends Component
|
|||||||
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
||||||
ex_alu_out)))).toBits; // WB_ALU
|
Mux(ex_reg_ctrl_sel_wb === WB_VEC, vec.io.appvl,
|
||||||
|
ex_alu_out))))).toBits; // WB_ALU
|
||||||
|
|
||||||
// memory stage
|
// memory stage
|
||||||
mem_reg_pc <== ex_reg_pc;
|
mem_reg_pc <== ex_reg_pc;
|
||||||
|
mem_reg_inst <== ex_reg_inst
|
||||||
|
mem_reg_rs2 <== ex_reg_rs2
|
||||||
mem_reg_waddr <== ex_reg_waddr;
|
mem_reg_waddr <== ex_reg_waddr;
|
||||||
mem_reg_wdata <== ex_wdata;
|
mem_reg_wdata <== ex_wdata;
|
||||||
|
mem_reg_raddr1 <== ex_reg_raddr1
|
||||||
mem_reg_raddr2 <== ex_reg_raddr2;
|
mem_reg_raddr2 <== ex_reg_raddr2;
|
||||||
mem_reg_ctrl_mul_val <== ex_reg_ctrl_mul_val;
|
mem_reg_ctrl_mul_val <== ex_reg_ctrl_mul_val;
|
||||||
mem_reg_ctrl_div_val <== ex_reg_ctrl_div_val;
|
mem_reg_ctrl_div_val <== ex_reg_ctrl_div_val;
|
||||||
|
|
||||||
when (io.ctrl.killx) {
|
when (io.ctrl.killx) {
|
||||||
mem_reg_valid <== Bool(false);
|
mem_reg_valid <== Bool(false);
|
||||||
mem_reg_ctrl_wen_pcr <== Bool(false);
|
mem_reg_ctrl_wen_pcr <== Bool(false);
|
||||||
@ -382,9 +398,12 @@ class rocketDpath extends Component
|
|||||||
(dmem_resp_replay || div_result_val || mul_result_val)
|
(dmem_resp_replay || div_result_val || mul_result_val)
|
||||||
|
|
||||||
wb_reg_pc <== mem_reg_pc;
|
wb_reg_pc <== mem_reg_pc;
|
||||||
|
wb_reg_inst <== mem_reg_inst
|
||||||
wb_reg_ll_wb <== mem_ll_wb
|
wb_reg_ll_wb <== mem_ll_wb
|
||||||
|
wb_reg_rs2 <== mem_reg_rs2
|
||||||
wb_reg_waddr <== mem_ll_waddr
|
wb_reg_waddr <== mem_ll_waddr
|
||||||
wb_reg_wdata <== mem_ll_wdata
|
wb_reg_wdata <== mem_ll_wdata
|
||||||
|
wb_reg_raddr1 <== mem_reg_raddr1
|
||||||
wb_reg_raddr2 <== mem_reg_raddr2;
|
wb_reg_raddr2 <== mem_reg_raddr2;
|
||||||
|
|
||||||
when (io.ctrl.killm) {
|
when (io.ctrl.killm) {
|
||||||
@ -409,6 +428,21 @@ class rocketDpath extends Component
|
|||||||
|
|
||||||
io.ctrl.wb_waddr := wb_reg_waddr;
|
io.ctrl.wb_waddr := wb_reg_waddr;
|
||||||
io.ctrl.mem_wb := dmem_resp_replay;
|
io.ctrl.mem_wb := dmem_resp_replay;
|
||||||
|
|
||||||
|
// vector datapath
|
||||||
|
vec.io.valid := wb_reg_valid
|
||||||
|
vec.io.sr_ev := pcr.io.status(SR_EV)
|
||||||
|
vec.io.inst := wb_reg_inst
|
||||||
|
vec.io.waddr := wb_reg_waddr
|
||||||
|
vec.io.raddr1 := wb_reg_raddr1
|
||||||
|
vec.io.vecbank := pcr.io.vecbank
|
||||||
|
vec.io.vecbankcnt := pcr.io.vecbankcnt
|
||||||
|
vec.io.wdata := wb_reg_wdata
|
||||||
|
vec.io.rs2 := wb_reg_rs2
|
||||||
|
|
||||||
|
vec.io.vcmdq <> io.vcmdq
|
||||||
|
vec.io.vximm1q <> io.vximm1q
|
||||||
|
vec.io.vximm2q <> io.vximm2q
|
||||||
|
|
||||||
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
||||||
io.ctrl.sboard_clr := mem_ll_wb
|
io.ctrl.sboard_clr := mem_ll_wb
|
||||||
|
|||||||
@ -62,6 +62,8 @@ class ioDpathPCR extends Bundle()
|
|||||||
val irq_ipi = Bool(OUTPUT);
|
val irq_ipi = Bool(OUTPUT);
|
||||||
val console_data = Bits(8, OUTPUT);
|
val console_data = Bits(8, OUTPUT);
|
||||||
val console_val = Bool(OUTPUT);
|
val console_val = Bool(OUTPUT);
|
||||||
|
val vecbank = Bits(8, OUTPUT)
|
||||||
|
val vecbankcnt = UFix(4, OUTPUT)
|
||||||
}
|
}
|
||||||
|
|
||||||
class rocketDpathPCR extends Component
|
class rocketDpathPCR extends Component
|
||||||
@ -79,6 +81,7 @@ class rocketDpathPCR extends Component
|
|||||||
val reg_k0 = Reg() { Bits() };
|
val reg_k0 = Reg() { Bits() };
|
||||||
val reg_k1 = Reg() { Bits() };
|
val reg_k1 = Reg() { Bits() };
|
||||||
val reg_ptbr = Reg() { UFix() };
|
val reg_ptbr = Reg() { UFix() };
|
||||||
|
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
|
||||||
|
|
||||||
val reg_error_mode = Reg(resetVal = Bool(false));
|
val reg_error_mode = Reg(resetVal = Bool(false));
|
||||||
val reg_status_vm = Reg(resetVal = Bool(false));
|
val reg_status_vm = Reg(resetVal = Bool(false));
|
||||||
@ -106,6 +109,12 @@ class rocketDpathPCR extends Component
|
|||||||
io.debug.error_mode := reg_error_mode;
|
io.debug.error_mode := reg_error_mode;
|
||||||
io.r.data := rdata;
|
io.r.data := rdata;
|
||||||
|
|
||||||
|
io.vecbank := reg_vecbank
|
||||||
|
var cnt = UFix(0)
|
||||||
|
for (i <- 0 until 8)
|
||||||
|
cnt = cnt + reg_vecbank(i)
|
||||||
|
io.vecbankcnt := cnt(3,0)
|
||||||
|
|
||||||
val console_wen = !io.exception && io.w.en && (io.w.addr === PCR_CONSOLE);
|
val console_wen = !io.exception && io.w.en && (io.w.addr === PCR_CONSOLE);
|
||||||
io.console_data := Mux(console_wen, io.w.data(7,0), Bits(0,8));
|
io.console_data := Mux(console_wen, io.w.data(7,0), Bits(0,8));
|
||||||
io.console_val := console_wen;
|
io.console_val := console_wen;
|
||||||
@ -176,6 +185,7 @@ class rocketDpathPCR extends Component
|
|||||||
when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
|
when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
|
||||||
when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; }
|
when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; }
|
||||||
when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
|
when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
|
||||||
|
when (io.w.addr === PCR_VECBANK) { reg_vecbank <== io.w.data(7,0) }
|
||||||
}
|
}
|
||||||
|
|
||||||
otherwise {
|
otherwise {
|
||||||
@ -202,6 +212,7 @@ class rocketDpathPCR extends Component
|
|||||||
is (PCR_K0) { rdata <== reg_k0; }
|
is (PCR_K0) { rdata <== reg_k0; }
|
||||||
is (PCR_K1) { rdata <== reg_k1; }
|
is (PCR_K1) { rdata <== reg_k1; }
|
||||||
is (PCR_PTBR) { rdata <== Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
|
is (PCR_PTBR) { rdata <== Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
|
||||||
|
is (PCR_VECBANK) { rdata <== Cat(Bits(0, 56), reg_vecbank) }
|
||||||
otherwise { rdata <== Bits(0,64); }
|
otherwise { rdata <== Bits(0,64); }
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
179
rocket/src/main/scala/dpath_vec.scala
Normal file
179
rocket/src/main/scala/dpath_vec.scala
Normal file
@ -0,0 +1,179 @@
|
|||||||
|
package Top
|
||||||
|
|
||||||
|
import Chisel._
|
||||||
|
import Node._
|
||||||
|
import Constants._
|
||||||
|
import Instructions._
|
||||||
|
import hwacha._
|
||||||
|
|
||||||
|
class ioDpathVec extends Bundle
|
||||||
|
{
|
||||||
|
val valid = Bool(INPUT)
|
||||||
|
val sr_ev = Bool(INPUT)
|
||||||
|
val inst = Bits(32, INPUT)
|
||||||
|
val waddr = UFix(5, INPUT)
|
||||||
|
val raddr1 = UFix(5, INPUT)
|
||||||
|
val vecbank = Bits(8, INPUT)
|
||||||
|
val vecbankcnt = UFix(4, INPUT)
|
||||||
|
val wdata = Bits(64, INPUT)
|
||||||
|
val rs2 = Bits(64, INPUT)
|
||||||
|
val appvl = UFix(12, OUTPUT)
|
||||||
|
val vcmdq = new io_vec_cmdq()
|
||||||
|
val vximm1q = new io_vec_ximm1q()
|
||||||
|
val vximm2q = new io_vec_ximm2q()
|
||||||
|
}
|
||||||
|
|
||||||
|
class rocketDpathVec extends Component
|
||||||
|
{
|
||||||
|
val io = new ioDpathVec()
|
||||||
|
|
||||||
|
val veccs =
|
||||||
|
ListLookup(io.inst,
|
||||||
|
// appvlmask
|
||||||
|
// | vcmdq
|
||||||
|
// wen | | vximm1q
|
||||||
|
// val vcmd vimm | fn | | | vximm2q
|
||||||
|
// | | | | | | | | |
|
||||||
|
List(N,VCMD_X, VIMM_X, N,VEC_X ,N,N,N,N),Array(
|
||||||
|
VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,Y,VEC_CFG,N,Y,Y,N),
|
||||||
|
VSETVL-> List(Y,VCMD_I, VIMM_VLEN,Y,VEC_VL ,N,Y,Y,N),
|
||||||
|
VF-> List(Y,VCMD_I, VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VMVV-> List(Y,VCMD_TX,VIMM_X, N,VEC_X ,Y,Y,N,N),
|
||||||
|
VMSV-> List(Y,VCMD_TX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VFMVV-> List(Y,VCMD_TF,VIMM_X, N,VEC_X ,Y,Y,N,N),
|
||||||
|
FENCE_L_V-> List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
|
||||||
|
FENCE_G_V-> List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
|
||||||
|
FENCE_L_CV->List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
|
||||||
|
FENCE_G_CV->List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
|
||||||
|
VLD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLWU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLHU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLBU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VSD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VSW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VSH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VSB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VFLD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VFLW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VFSD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VFSW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
|
||||||
|
VLSTD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VSSTD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VSSTW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VSSTH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VSSTB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
|
||||||
|
VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y)
|
||||||
|
))
|
||||||
|
|
||||||
|
val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
|
||||||
|
val wb_vec_cmdq_val :: wb_vec_ximm1q_val :: wb_vec_ximm2q_val :: Nil = veccs0
|
||||||
|
|
||||||
|
val nxregs = io.inst(15,10)
|
||||||
|
val nfregs = io.inst(21,16)
|
||||||
|
val nregs = (nxregs + nfregs)(6,0)
|
||||||
|
|
||||||
|
val uts_per_bank = MuxLookup(
|
||||||
|
nregs, UFix(4,9), Array(
|
||||||
|
UFix(0,7) -> UFix(256,9),
|
||||||
|
UFix(1,7) -> UFix(256,9),
|
||||||
|
UFix(2,7) -> UFix(256,9),
|
||||||
|
UFix(3,7) -> UFix(128,9),
|
||||||
|
UFix(4,7) -> UFix(85,9),
|
||||||
|
UFix(5,7) -> UFix(64,9),
|
||||||
|
UFix(6,7) -> UFix(51,9),
|
||||||
|
UFix(7,7) -> UFix(42,9),
|
||||||
|
UFix(8,7) -> UFix(36,9),
|
||||||
|
UFix(9,7) -> UFix(32,9),
|
||||||
|
UFix(10,7) -> UFix(28,9),
|
||||||
|
UFix(11,7) -> UFix(25,9),
|
||||||
|
UFix(12,7) -> UFix(23,9),
|
||||||
|
UFix(13,7) -> UFix(21,9),
|
||||||
|
UFix(14,7) -> UFix(19,9),
|
||||||
|
UFix(15,7) -> UFix(18,9),
|
||||||
|
UFix(16,7) -> UFix(17,9),
|
||||||
|
UFix(17,7) -> UFix(16,9),
|
||||||
|
UFix(18,7) -> UFix(15,9),
|
||||||
|
UFix(19,7) -> UFix(14,9),
|
||||||
|
UFix(20,7) -> UFix(13,9),
|
||||||
|
UFix(21,7) -> UFix(12,9),
|
||||||
|
UFix(22,7) -> UFix(12,9),
|
||||||
|
UFix(23,7) -> UFix(11,9),
|
||||||
|
UFix(24,7) -> UFix(11,9),
|
||||||
|
UFix(25,7) -> UFix(10,9),
|
||||||
|
UFix(26,7) -> UFix(10,9),
|
||||||
|
UFix(27,7) -> UFix(9,9),
|
||||||
|
UFix(28,7) -> UFix(9,9),
|
||||||
|
UFix(29,7) -> UFix(9,9),
|
||||||
|
UFix(30,7) -> UFix(8,9),
|
||||||
|
UFix(31,7) -> UFix(8,9),
|
||||||
|
UFix(32,7) -> UFix(8,9),
|
||||||
|
UFix(33,7) -> UFix(8,9),
|
||||||
|
UFix(34,7) -> UFix(7,9),
|
||||||
|
UFix(35,7) -> UFix(7,9),
|
||||||
|
UFix(36,7) -> UFix(7,9),
|
||||||
|
UFix(37,7) -> UFix(7,9),
|
||||||
|
UFix(38,7) -> UFix(6,9),
|
||||||
|
UFix(39,7) -> UFix(6,9),
|
||||||
|
UFix(40,7) -> UFix(6,9),
|
||||||
|
UFix(41,7) -> UFix(6,9),
|
||||||
|
UFix(42,7) -> UFix(6,9),
|
||||||
|
UFix(43,7) -> UFix(6,9),
|
||||||
|
UFix(44,7) -> UFix(5,9),
|
||||||
|
UFix(45,7) -> UFix(5,9),
|
||||||
|
UFix(46,7) -> UFix(5,9),
|
||||||
|
UFix(47,7) -> UFix(5,9),
|
||||||
|
UFix(48,7) -> UFix(5,9),
|
||||||
|
UFix(49,7) -> UFix(5,9),
|
||||||
|
UFix(50,7) -> UFix(5,9),
|
||||||
|
UFix(51,7) -> UFix(5,9),
|
||||||
|
UFix(52,7) -> UFix(5,9)
|
||||||
|
))
|
||||||
|
|
||||||
|
val reg_hwvl = Reg(resetVal = UFix(32, 12))
|
||||||
|
val reg_appvl0 = Reg(resetVal = Bool(true))
|
||||||
|
val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)
|
||||||
|
val hwvl = Mux(wb_vec_fn.toBool, hwvl_vcfg, reg_hwvl)
|
||||||
|
val appvl = Mux(io.wdata(11,0) < hwvl, io.wdata(11,0), hwvl).toUFix
|
||||||
|
|
||||||
|
when (io.valid && wb_vec_wen.toBool && wb_vec_fn.toBool)
|
||||||
|
{
|
||||||
|
reg_hwvl <== hwvl_vcfg
|
||||||
|
reg_appvl0 <== !(appvl.orR())
|
||||||
|
}
|
||||||
|
|
||||||
|
io.appvl := appvl
|
||||||
|
val vlenm1 = appvl - Bits(1,1)
|
||||||
|
|
||||||
|
val valid_common = io.valid && io.sr_ev && wb_vec_val.toBool && !(wb_vec_appvlmask.toBool && reg_appvl0)
|
||||||
|
|
||||||
|
io.vcmdq.valid := valid_common && wb_vec_cmdq_val
|
||||||
|
io.vximm1q.valid := valid_common && wb_vec_ximm1q_val
|
||||||
|
io.vximm2q.valid := valid_common && wb_vec_ximm2q_val
|
||||||
|
|
||||||
|
io.vcmdq.bits :=
|
||||||
|
Mux(wb_sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
|
||||||
|
Mux(wb_sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
|
||||||
|
Mux(wb_sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
|
||||||
|
Mux(wb_sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), io.waddr, Bits(1,1), io.raddr1),
|
||||||
|
Mux(wb_sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), io.waddr, Bits(0,1), io.waddr),
|
||||||
|
Mux(wb_sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), io.waddr, Bits(1,1), io.waddr),
|
||||||
|
Bits(0,20)))))))
|
||||||
|
|
||||||
|
io.vximm1q.bits :=
|
||||||
|
Mux(wb_sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1),
|
||||||
|
io.wdata) // VIMM_ALU
|
||||||
|
|
||||||
|
io.vximm2q.bits := io.rs2
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user