riscv/rocket-chip
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hook up the vector command queue

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This commit is contained in:
Yunsup Lee
2012-02-09 01:28:16 -08:00
parent 8b6b0f5367
commit fcc8081c4d
6 changed files with 396 additions and 180 deletions
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12
rocket/src/main/scala/consts.scala
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@ -65,6 +65,7 @@ object Constants
val WB_ALU = UFix(2, 3);
val WB_TSC = UFix(4, 3);
val WB_IRT = UFix(5, 3);
val WB_VEC = UFix(6, 3);
val N = UFix(0, 1);
val Y = UFix(1, 1);
@ -146,8 +147,8 @@ object Constants
val PCR_K1 = UFix(13, 5);
val PCR_TOHOST = UFix(16, 5);
val PCR_FROMHOST = UFix(17, 5);
val PCR_CONSOLE = UFix(18, 5);
val PCR_VECBANK = UFix(18, 5);
val PCR_CONSOLE = UFix(19, 5);
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps
@ -222,10 +223,9 @@ object Constants
val VCMD_MF = UFix(5, 3)
val VCMD_X = UFix(0, 3)
val VIMM_VLEN = UFix(0, 2)
val VIMM_ALU = UFix(1, 2)
val VIMM_RS1 = UFix(2, 2)
val VIMM_X = UFix(0, 2)
val VIMM_VLEN = UFix(0, 1)
val VIMM_ALU = UFix(1, 1)
val VIMM_X = UFix(0, 1)
}
}