riscv/rocket-chip
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Print out the compressed instruction when executing one

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This commit is contained in:
Palmer Dabbelt
2017-08-07 17:21:08 -07:00
parent e27072e063
commit fc0d5fcf98
2 changed files with 15 additions and 5 deletions
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2
src/main/scala/rocket/IBuf.scala
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@ -16,6 +16,7 @@ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with H
val rvc = Bool()
val inst = new ExpandedInstruction
val raw = UInt(width = 32)
val cinst = UInt(width = 32)
require(coreInstBits == (if (usingCompressed) 16 else 32))
}
@ -95,6 +96,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
exp.io.in := curInst
io.inst(i).bits.inst := exp.io.out
io.inst(i).bits.raw := curInst
io.inst(i).bits.cinst := Mux(exp.io.rvc, curInst & 0xFFFF, curInst)
if (usingCompressed) {
val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))