riscv/rocket-chip
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fixed eret instruction

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This commit is contained in:
Rimas Avizienis 2011-11-10 00:37:00 -08:00
parent 62407b4668
commit fbfa356d2a
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -350,7 +350,7 @@ class rocketCtrl extends Component
// FIXME: dtlb exception handling broken, need to move cause value generation
// to mem stage. also should probably move it from dpath to ctrl
io.dpath.sel_pc :=
Mux(io.dpath.exception || io.dtlb_xcpt, PC_PCR,
Mux(io.dpath.exception || io.dtlb_xcpt || mem_reg_eret, PC_PCR,
Mux(replay_ex || replay_mem || mem_reg_privileged, PC_EX,
Mux(!ex_reg_btb_hit && br_taken, PC_BR,
Mux(ex_reg_btb_hit && !br_taken, PC_EX4,