riscv/rocket-chip
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Use Reg(Vec) instead of Seq(Reg) for DCache MMIO

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This commit is contained in:
Andrew Waterman
2017-03-23 13:17:54 -07:00
parent 0538dc77ce
commit fb6498f2c3
1 changed files with 8 additions and 17 deletions
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25
src/main/scala/rocket/DCache.scala
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@@ -87,8 +87,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack
// I/O MSHRs // I/O MSHRs
val uncachedInFlight = Seq.fill(cacheParams.nMMIOs) { RegInit(Bool(false)) } val uncachedInFlight = Reg(init = Vec.fill(cacheParams.nMMIOs)(false.B))
val uncachedReqs = Seq.fill(cacheParams.nMMIOs) { Reg(new HellaCacheReq) } val uncachedReqs = Reg(Vec(cacheParams.nMMIOs, new HellaCacheReq))
// hit initiation path // hit initiation path
dataArb.io.in(3).valid := io.cpu.req.valid && isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && isRead(io.cpu.req.bits.cmd)
@@ -284,15 +284,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tl_out.a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics))) tl_out.a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics)))
// Set pending bits for outstanding TileLink transaction // Set pending bits for outstanding TileLink transaction
val a_sel = UIntToOH(a_source, cacheParams.nMMIOs)
when (tl_out.a.fire()) { when (tl_out.a.fire()) {
when (s2_uncached) { when (s2_uncached) {
(a_sel.toBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => uncachedInFlight(a_source) := true
when (s) { uncachedReqs(a_source) := s2_req
f := Bool(true)
r := s2_req
}
}
}.otherwise { }.otherwise {
cached_grant_wait := true cached_grant_wait := true
} }
@@ -311,14 +306,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") assert(cached_grant_wait, "A GrantData was unexpected by the dcache.")
when(d_last) { cached_grant_wait := false } when(d_last) { cached_grant_wait := false }
} .elsewhen (grantIsUncached) { } .elsewhen (grantIsUncached) {
val d_sel = UIntToOH(tl_out.d.bits.source, cacheParams.nMMIOs) assert(d_last, "DCache MMIO responses must be single-beat")
val req = Mux1H(d_sel, uncachedReqs) assert(uncachedInFlight(tl_out.d.bits.source), "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
(d_sel.toBools zip uncachedInFlight) foreach { case (s, f) => uncachedInFlight(tl_out.d.bits.source) := false
when (s && d_last) { val req = uncachedReqs(tl_out.d.bits.source)
assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
f := false
}
}
when (grantIsUncachedData) { when (grantIsUncachedData) {
s2_data := tl_out.d.bits.data s2_data := tl_out.d.bits.data
s2_req.cmd := req.cmd s2_req.cmd := req.cmd