From fb4408b150e2b2b88a234c3ca855638c39bce084 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Sun, 15 Apr 2012 22:56:02 -0700
Subject: [PATCH] fix AMO replay/coherence deadlock

---
 rocket/src/main/scala/nbdcache.scala | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 3a4bb0ab..0ecfc6ad 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -809,6 +809,9 @@ class HellaCache(co: CoherencePolicy) extends Component {
     r_cpu_req_type := io.cpu.req_type
     r_cpu_req_tag  := io.cpu.req_tag
   }
+  when (prober.io.meta_req.valid) {
+    r_cpu_req_idx := Cat(prober.io.meta_req.bits.data.tag, prober.io.meta_req.bits.idx, mshr.io.data_req.bits.offset)(PGIDX_BITS-1,0)
+  }
   when (replay_amo_val) {
     r_cpu_req_idx  := Cat(mshr.io.data_req.bits.idx, mshr.io.data_req.bits.offset)
     r_cpu_req_cmd  := mshr.io.data_req.bits.cmd
@@ -816,9 +819,6 @@ class HellaCache(co: CoherencePolicy) extends Component {
     r_amo_replay_data := mshr.io.data_req.bits.data
     r_way_oh       := mshr.io.data_req.bits.way_oh
   }
-  when (prober.io.meta_req.valid) {
-    r_cpu_req_idx := Cat(prober.io.meta_req.bits.data.tag, prober.io.meta_req.bits.idx, mshr.io.data_req.bits.offset)(PGIDX_BITS-1,0)
-  }
   when (flusher.io.meta_req.valid) {
     r_cpu_req_idx := Cat(flusher.io.meta_req.bits.idx, mshr.io.data_req.bits.offset)
     r_cpu_req_cmd := M_FLA
@@ -869,15 +869,6 @@ class HellaCache(co: CoherencePolicy) extends Component {
   wb.io.data_resp <> data_resp_mux
   wb.io.probe_rep_data <> io.mem.probe_rep_data
 
-  // probes
-  prober.io.req <> io.mem.probe_req
-  prober.io.rep <> io.mem.probe_rep
-  prober.io.meta_req <> meta_arb.io.in(2)
-  prober.io.mshr_req <> mshr.io.probe
-  prober.io.wb_req <> wb.io.probe
-  prober.io.tag_match_way_oh := tag_match_way_oh
-  prober.io.line_state := meta_resp_mux.state
-
   // replacement policy
   val replacer = new RandomReplacementWayGen()
   replacer.io.way_en := ~UFix(0, NWAYS)
@@ -964,7 +955,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
 
   // replays
   val replay = mshr.io.data_req.bits
-  val stall_replay = r_replay_amo || p_amo || flusher.io.meta_req.valid || prober.io.meta_req.valid || p_store_valid
+  val stall_replay = r_replay_amo || p_amo || flusher.io.meta_req.valid || p_store_valid
   val replay_val = mshr.io.data_req.valid
   val replay_fire = replay_val && !stall_replay
   val replay_rdy = data_arb.io.in(1).ready && !stall_replay
@@ -976,6 +967,17 @@ class HellaCache(co: CoherencePolicy) extends Component {
   mshr.io.data_req.ready := replay_rdy
   r_replay_amo := replay_amo_val && replay_rdy
 
+  // probes
+  prober.io.req <> io.mem.probe_req
+  prober.io.rep <> io.mem.probe_rep
+  prober.io.mshr_req <> mshr.io.probe
+  prober.io.wb_req <> wb.io.probe
+  prober.io.tag_match_way_oh := tag_match_way_oh
+  prober.io.line_state := meta_resp_mux.state
+  prober.io.meta_req.ready := meta_arb.io.in(2).ready && !replay_amo_val
+  meta_arb.io.in(2).valid := prober.io.meta_req.valid
+  meta_arb.io.in(2).bits := prober.io.meta_req.bits
+
   // store write mask generation.
   // assumes store replays are higher-priority than pending stores.
   val maskgen = new StoreMaskGen