rocketchip: globals are for sissies

src/main/scala/coreplex/Configs.scala

@@ -146,7 +146,7 @@ class BaseCoreplexConfig extends Config (
             else new MESICoherence(site(L2DirectoryRepresentation))),
           nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
           nCachingClients = site(NCachedTileLinkPorts),
-          nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
+          nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
           maxClientXacts = max_int(
               // L1 cache
               site(DCacheKey).nMSHRs + 1 /* IOMSHR */,

src/main/scala/coreplex/Coreplex.scala

@@ -32,7 +32,7 @@ trait HasCoreplexParameters {
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
   lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
   lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
-  lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
+  lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
 }
 
 case class CoreplexConfig(

src/main/scala/coreplex/TestConfigs.scala

@@ -24,7 +24,7 @@ class WithComparator extends Config(
       (p: Parameters) => Module(new ComparatorCore()(p))
     case ComparatorKey => ComparatorParameters(
       targets    = Seq("mem", "io:ext:testram").map(name =>
-                    site(GlobalAddrMap).get(name).start.longValue),
+                    site(GlobalAddrMap)(name).start.longValue),
       width      = 8,
       operations = 1000,
       atomics    = site(UseAtomics),
@@ -54,7 +54,7 @@ class WithMemtest extends Config(
     }
     case GeneratorKey => GeneratorParameters(
       maxRequests = 128,
-      startAddress = site(GlobalAddrMap).get("mem").start)
+      startAddress = site(GlobalAddrMap)("mem").start)
     case BuildGroundTest =>
       (p: Parameters) => Module(new GeneratorTest()(p))
     case _ => throw new CDEMatchError
@@ -114,7 +114,7 @@ class WithNastiConverterTest extends Config(
     }
     case GeneratorKey => GeneratorParameters(
       maxRequests = 128,
-      startAddress = site(GlobalAddrMap).get("mem").start)
+      startAddress = site(GlobalAddrMap)("mem").start)
     case BuildGroundTest =>
       (p: Parameters) => Module(new NastiConverterTest()(p))
     case _ => throw new CDEMatchError
@@ -134,7 +134,7 @@ class WithTraceGen extends Config(
       val nSets = 32 // L2 NSets
       val nWays = 1
       val blockOffset = site(CacheBlockOffsetBits)
-      val baseAddr = site(GlobalAddrMap).get("mem").start
+      val baseAddr = site(GlobalAddrMap)("mem").start
       val nBeats = site(MIFDataBeats)
       List.tabulate(4 * nWays) { i =>
         Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
@@ -157,7 +157,7 @@ class WithPCIeMockupTest extends Config(
       GroundTestTileSettings(1))
     case GeneratorKey => GeneratorParameters(
       maxRequests = 128,
-      startAddress = site(GlobalAddrMap).get("mem").start)
+      startAddress = site(GlobalAddrMap)("mem").start)
     case BuildGroundTest =>
       (p: Parameters) => p(TileId) match {
         case 0 => Module(new GeneratorTest()(p))

src/main/scala/junctions/addrmap.scala

@@ -12,7 +12,7 @@ trait HasAddrMapParameters {
   implicit val p: Parameters
 
   val paddrBits = p(PAddrBits)
-  def addrMap = p(rocketchip.GlobalAddrMap).get
+  def addrMap = p(rocketchip.GlobalAddrMap)
 }
 
 case class MemAttr(prot: Int, cacheable: Boolean = false)

src/main/scala/rocketchip/Configs.scala

@@ -20,9 +20,6 @@ import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 
 class BasePlatformConfig extends Config(
   topDefinitions = {
-    val configString = new GlobalVariable[String]
-    val globalAddrMap = new GlobalVariable[AddrMap]
-    val nCoreplexExtClients = new GlobalVariable[Int]
     (pname,site,here) =>  {
       type PF = PartialFunction[Any,Any]
       def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
@@ -55,7 +52,6 @@ class BasePlatformConfig extends Config(
         case NExtMMIOTLChannels  => 0
         case AsyncBusChannels => false
         case NExtBusAXIChannels => 0
-        case NCoreplexExtClients => nCoreplexExtClients
         case HastiId => "Ext"
         case HastiKey("TL") =>
           HastiParameters(
@@ -69,8 +65,6 @@ class BasePlatformConfig extends Config(
         case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
         case TMemoryChannels => BusType.AXI
         case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
-        case ConfigString => configString
-        case GlobalAddrMap => globalAddrMap
         case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
         case BuildExampleTop =>
           (p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTop(p))

src/main/scala/rocketchip/Generator.scala

@@ -56,6 +56,10 @@ trait HasGeneratorUtilities {
   }
 }
 
+object ConfigStringOutput {
+  var contents: Option[String] = None
+}
+
 trait Generator extends App with HasGeneratorUtilities {
   lazy val names = {
     require(args.size == 5, "Usage: sbt> " + 
@@ -67,20 +71,25 @@ trait Generator extends App with HasGeneratorUtilities {
       configProject = args(3),
       configs = args(4))
   }
+
+  lazy val td = names.targetDir
   lazy val config = getConfig(names)
   lazy val world = config.toInstance
   lazy val params = Parameters.root(world)
   lazy val circuit = elaborate(names, params)
+  lazy val longName = names.topModuleClass + "." + names.configs
+
+  def writeOutputFiles() {
+    TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
+    writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
+    writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
+    writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
+    writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
+    ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software
+  }
 }
 
 object RocketChipGenerator extends Generator {
-  val longName = names.topModuleClass + "." + names.configs
-  val td = names.targetDir
   Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
-  TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
+  writeOutputFiles()
-  writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
-  writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
-  writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
-  writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
-  writeOutputFile(td, s"${names.configs}.cfg", params(ConfigString).get) // String for software
 }

src/main/scala/rocketchip/TestConfigs.scala

@@ -27,7 +27,7 @@ class WithGroundTest extends Config(
           else new MESICoherence(site(L2DirectoryRepresentation))),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
         nCachingClients = site(NCachedTileLinkPorts),
-        nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
+        nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
         maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
                            site(GroundTestKey).map(_.maxXacts))
                              .reduce(max(_, _)),

src/main/scala/rocketchip/TestHarness.scala

@@ -11,11 +11,12 @@ import junctions.NastiConstants._
 case object BuildExampleTop extends Field[Parameters => ExampleTop]
 case object SimMemLatency extends Field[Int]
 
-class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapParameters {
+class TestHarness(q: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)
   }
-  val dut = p(BuildExampleTop)(p).module
+  val dut = q(BuildExampleTop)(q).module
+  implicit val p = dut.p
 
   // This test harness isn't especially flexible yet
   require(dut.io.mem_clk.isEmpty)
@@ -33,7 +34,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapPara
     int := false
 
   if (dut.io.mem_axi.nonEmpty) {
-    val memSize = addrMap("mem").size
+    val memSize = p(GlobalAddrMap)("mem").size
     require(memSize % dut.io.mem_axi.size == 0)
     for (axi <- dut.io.mem_axi) {
       val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi.size))

src/main/scala/rocketchip/Top.scala

@@ -14,18 +14,37 @@ import rocket.Util._
 import coreplex._
 
 // the following parameters will be refactored properly with TL2
-case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
+case object GlobalAddrMap extends Field[AddrMap]
-case object ConfigString extends Field[GlobalVariable[String]]
+case object ConfigString extends Field[String]
-case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
+case object NCoreplexExtClients extends Field[Int]
 /** Function for building Coreplex */
 case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
 
 /** Base Top with no Periphery */
-abstract class BaseTop(val p: Parameters) extends LazyModule {
+abstract class BaseTop(q: Parameters) extends LazyModule {
   // the following variables will be refactored properly with TL2
   val pInterrupts = new RangeManager
   val pBusMasters = new RangeManager
   val pDevices = new ResourceManager[AddrMapEntry]
+
+  lazy val c = CoreplexConfig(
+    nTiles = q(NTiles),
+    nExtInterrupts = pInterrupts.sum,
+    nSlaves = pBusMasters.sum,
+    nMemChannels = q(NMemoryChannels),
+    hasSupervisor = q(UseVM),
+    hasExtMMIOPort = true
+  )
+
+  lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get)
+  private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
+
+  lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get)
+  implicit val p = qWithMap.alterPartial({
+    case ConfigString => genConfigString
+    case NCoreplexExtClients => pBusMasters.sum})
+
+  // Add a peripheral bus
   val peripheryBus = LazyModule(new TLXbar)
   val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
 
@@ -39,24 +58,19 @@ class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBun
 class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
   val outer: L = l
 
-  val c = CoreplexConfig(
+  val coreplex = p(BuildCoreplex)(p, outer.c)
-    nTiles = p(NTiles),
+  val io: B = b(coreplex)
-    nExtInterrupts = outer.pInterrupts.sum,
-    nSlaves = outer.pBusMasters.sum,
-    nMemChannels = p(NMemoryChannels),
-    hasSupervisor = p(UseVM),
-    hasExtMMIOPort = true
-  )
 
-  def genGlobalAddrMap = GenerateGlobalAddrMap(p, outer.pDevices.get)
+  io.success zip coreplex.io.success map { case (x, y) => x := y }
-  def genConfigString = GenerateConfigString(p, c, outer.pDevices.get)
 
-  p(NCoreplexExtClients).assign(outer.pBusMasters.sum)
+  val mmioNetwork =
-  p(GlobalAddrMap).assign(genGlobalAddrMap)
+    Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
-  p(ConfigString).assign(genConfigString)
+      p.alterPartial({ case TLId => "L2toMMIO" })))
+  mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
+  outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
 
   println("Generated Address Map")
-  for (entry <- p(GlobalAddrMap).get.flatten) {
+  for (entry <- p(GlobalAddrMap).flatten) {
     val name = entry.name
     val start = entry.region.start
     val end = entry.region.start + entry.region.size - 1
@@ -64,22 +78,12 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   }
 
   println("Generated Configuration String")
-  println(p(ConfigString).get)
+  println(p(ConfigString))
-
+  ConfigStringOutput.contents = Some(p(ConfigString))
-  val coreplex = p(BuildCoreplex)(p, c)
-  val io: B = b(coreplex)
-
-  io.success zip coreplex.io.success map { case (x, y) => x := y }
-
-  val mmioNetwork =
-    Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
-      p.alterPartial({ case TLId => "L2toMMIO" })))
-  mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
-  outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
 }
 
 /** Example Top with Periphery */
-class ExampleTop(p: Parameters) extends BaseTop(p)
+class ExampleTop(q: Parameters) extends BaseTop(q)
     with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
     with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
   override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
@@ -94,7 +98,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters,
     with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
 
 /** Example Top with TestRAM */
-class ExampleTopWithTestRAM(p: Parameters) extends ExampleTop(p)
+class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
     with PeripheryTestRAM {
   override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
 }

src/main/scala/rocketchip/UnitTest.scala

@@ -36,10 +36,10 @@ class UnitTestHarness(implicit val p: Parameters) extends Module {
     val success = Bool(OUTPUT)
   }
 
-  p(NCoreplexExtClients).assign(0)
+  val l1params = p.alterPartial({
-  p(ConfigString).assign("")
+    case NCoreplexExtClients => 0
-
+    case ConfigString => ""
-  val l1params = p.alterPartial({ case TLId => "L1toL2" })
+    case TLId => "L1toL2" })
   val tests = Module(new UnitTestSuite()(l1params))
 
   io.success := tests.io.finished

src/main/scala/rocketchip/Utils.scala

@@ -81,7 +81,7 @@ object GenerateGlobalAddrMap {
 
 object GenerateConfigString {
   def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
-    val addrMap = p(GlobalAddrMap).get
+    val addrMap = p(GlobalAddrMap)
     val plicAddr = addrMap("io:int:plic").start
     val prciAddr = addrMap("io:ext:TL2:prci").start
     val xLen = p(XLen)
@@ -156,8 +156,8 @@ object GenerateBootROM {
 
     // for now, have the reset vector jump straight to memory
     val memBase = (
-      if (p(GlobalAddrMap).get contains "mem") p(GlobalAddrMap).get("mem")
+      if (p(GlobalAddrMap) contains "mem") p(GlobalAddrMap)("mem")
-      else p(GlobalAddrMap).get("io:int:dmem0")
+      else p(GlobalAddrMap)("io:int:dmem0")
     ).start
     val resetToMemDist = memBase - p(ResetVector)
     require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
@@ -166,6 +166,6 @@ object GenerateBootROM {
     require(rom.getInt(12) == 0,
       "Config string address position should not be occupied by code")
     rom.putInt(12, configStringAddr)
-    rom.array() ++ (p(ConfigString).get.getBytes.toSeq)
+    rom.array() ++ (p(ConfigString).getBytes.toSeq)
   }
 }