rocketchip: globals are for sissies

src/main/scala/rocketchip/Top.scala

@@ -14,18 +14,37 @@ import rocket.Util._
 import coreplex._
 
 // the following parameters will be refactored properly with TL2
-case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
-case object ConfigString extends Field[GlobalVariable[String]]
-case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
+case object GlobalAddrMap extends Field[AddrMap]
+case object ConfigString extends Field[String]
+case object NCoreplexExtClients extends Field[Int]
 /** Function for building Coreplex */
 case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
 
 /** Base Top with no Periphery */
-abstract class BaseTop(val p: Parameters) extends LazyModule {
+abstract class BaseTop(q: Parameters) extends LazyModule {
   // the following variables will be refactored properly with TL2
   val pInterrupts = new RangeManager
   val pBusMasters = new RangeManager
   val pDevices = new ResourceManager[AddrMapEntry]
+
+  lazy val c = CoreplexConfig(
+    nTiles = q(NTiles),
+    nExtInterrupts = pInterrupts.sum,
+    nSlaves = pBusMasters.sum,
+    nMemChannels = q(NMemoryChannels),
+    hasSupervisor = q(UseVM),
+    hasExtMMIOPort = true
+  )
+
+  lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get)
+  private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
+
+  lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get)
+  implicit val p = qWithMap.alterPartial({
+    case ConfigString => genConfigString
+    case NCoreplexExtClients => pBusMasters.sum})
+
+  // Add a peripheral bus
   val peripheryBus = LazyModule(new TLXbar)
   val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
 
@@ -39,24 +58,19 @@ class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBun
 class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
   val outer: L = l
 
-  val c = CoreplexConfig(
-    nTiles = p(NTiles),
-    nExtInterrupts = outer.pInterrupts.sum,
-    nSlaves = outer.pBusMasters.sum,
-    nMemChannels = p(NMemoryChannels),
-    hasSupervisor = p(UseVM),
-    hasExtMMIOPort = true
-  )
+  val coreplex = p(BuildCoreplex)(p, outer.c)
+  val io: B = b(coreplex)
 
-  def genGlobalAddrMap = GenerateGlobalAddrMap(p, outer.pDevices.get)
-  def genConfigString = GenerateConfigString(p, c, outer.pDevices.get)
+  io.success zip coreplex.io.success map { case (x, y) => x := y }
 
-  p(NCoreplexExtClients).assign(outer.pBusMasters.sum)
-  p(GlobalAddrMap).assign(genGlobalAddrMap)
-  p(ConfigString).assign(genConfigString)
+  val mmioNetwork =
+    Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
+      p.alterPartial({ case TLId => "L2toMMIO" })))
+  mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
+  outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
 
   println("Generated Address Map")
-  for (entry <- p(GlobalAddrMap).get.flatten) {
+  for (entry <- p(GlobalAddrMap).flatten) {
     val name = entry.name
     val start = entry.region.start
     val end = entry.region.start + entry.region.size - 1
@@ -64,22 +78,12 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   }
 
   println("Generated Configuration String")
-  println(p(ConfigString).get)
-
-  val coreplex = p(BuildCoreplex)(p, c)
-  val io: B = b(coreplex)
-
-  io.success zip coreplex.io.success map { case (x, y) => x := y }
-
-  val mmioNetwork =
-    Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
-      p.alterPartial({ case TLId => "L2toMMIO" })))
-  mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
-  outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
+  println(p(ConfigString))
+  ConfigStringOutput.contents = Some(p(ConfigString))
 }
 
 /** Example Top with Periphery */
-class ExampleTop(p: Parameters) extends BaseTop(p)
+class ExampleTop(q: Parameters) extends BaseTop(q)
     with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
     with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
   override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
@@ -94,7 +98,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters,
     with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
 
 /** Example Top with TestRAM */
-class ExampleTopWithTestRAM(p: Parameters) extends ExampleTop(p)
+class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
     with PeripheryTestRAM {
   override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
 }